公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Power Scan: DFT for Power Switches in VLSI Designs | CHIEN-MO LI | International Test Conference | | | |
2009 | Power scan: OFT for power switches in VLSI designs | Bai, B.-C.; Li, C.-M.; Kifli, A.; Tsai, E.; CHIEN-MO LI | Proceedings - International Test Conference | 0 | 0 | |
2014 | Power-Supply-Noise-Aware Dynamic Timing Analyzer for 3D IC | CHIEN-MO LI ; H.Y. Hsieh; CHIEN-MO LI | IEEE 3D IC Test Workshop | | | |
2016 | Power-supply-noise-aware timing analysis and test pattern regeneration | Han, C.-Y.; Li, Y.-C.; Kan, H.-T.; CHIEN-MO LI | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | | | |
2001 | Pseudo Random Testing Theoretical Models vs. Real Data | CHIEN-MO LI ; Mitra; S.; C.W. Tseng; J. C. M Li; E. J. McCluskey; CHIEN-MO LI | IEEE International Workshop on Test Resource Partitioning | | | |
2017 | PSN-aware Circuit Test Timing Prediction using Machine Learning | B. Liu; J. C.M. Li; CHIEN-MO LI | IET Computers & Digital Techniques | 9 | 6 | |
2011 | Reliability and Validity Evidence of the Chinese Piers-Harris Children's Self-Concept Scale Scores Among Taiwanese Children | Flahive, Mon-hsin Wang; Chuang, Ying-Chih; CHIEN-MO LI | Journal of Psychoeducational Assessment | | | |
2010 | Reliability screening of a-Si TFT circuits: Very-low voltage and I <inf>DDQ</inf> Testing | Shen, S.-T.; Liu, C.; Ma, E.-H.; Cheng, I.-C.; Li, J.C.-M.; I-CHUN CHENG ; CHIEN-MO LI | IEEE/OSA Journal of Display Technology | 2 | 1 | |
2007 | Response Inversion Scan Cell (RISC): A Peak Capture Power Reduction Technique | CHIEN-MO LI ; B.-H. Chen; Wei-Chuang Kao; Bin-Chuan Bai; Shyue-Tsong Shen; CHIEN-MO LI | IEEE Asian Test Symposium | | | |
2017 | Robust test pattern generation for hold-time faults in nanometer technologies | Ho, Y.-H.; Chen, Y.-W.; Chang, C.-M.; Yang, K.-C.; CHIEN-MO LI | 2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | | | |
2010 | Row-LFSR-Column (RLC) Test Response Masking Technique | CHIEN-MO LI ; WC Wang; CHIEN-MO LI | VLSI/CAD | | | |
2011 | Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips | CHIEN-MO LI ; W.C. Wang; CHIEN-MO LI | IET Computers & Digital Techniques | | 2 | |
2005 | Segmented Weighted Random BIST (SWR-BIST) Technique for Low Power Testing | CHIEN-MO LI ; Lee, C-Y; CHIEN-MO LI | Asia Solid-State Circuit Conference (ASSCC) | | | |
2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | CHIEN-MO LI ; H.T. Lin; CHIEN-MO LI | IET Computers & Digital Techniques | | | |
2014 | Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics | CHIEN-MO LI ; Y. L. Chen; W. R. Wu; C. N. J. Liu; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | 16 | |
2023 | Small Sampling Overhead Error Mitigation for Quantum Circuits | Hsieh, Cheng Yun; Tsai, Hsin Ying; Lu, Yuan Hsiang; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2010 | Static timing analysis for flexible TFT circuits | CHIEN-MO LI ; Chao-Hsuan Hsu; Liu, C.; En-Hua Ma; CHIEN-MO LI | Design Automation Conference (DAC) | | | |
2012 | Structural Reduction Techniques for Logic-Chain Bridging Fault Diagnosis | CHIEN-MO LI ; W.L. Tsai; CHIEN-MO LI | IEEE Transactions on Computers | | 9 | |
2020 | Student engagement in the co-designing and co-teaching a cornerstone eecs design and implementation course at national Taiwan university | Lee, Jennifer Wen-Shya et al.; Lin, Kun-You ; Chen, Ho-Lin ; Chen, J.-P.; SHIH-YUAN CHEN ; CHIEN-MO LI ; Xu, R.-F.; TZI-DAR CHIUEH ; HSIAO-WEN CHUNG ; Chen, N.; SHI-CHUNG CHANG | International Conference on Higher Education Advances | 0 | 0 | |
2008 | Survey of Scan Chain Diagnosis | CHIEN-MO LI ; Y. Huang; R Guo; W.T. Cheng; CHIEN-MO LI | IEEE Design & Test of Computers | | | |