公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2014 | Obstacle-avoiding free-assignment routing for flip-chip designs | Ho, Y.-K.; Lee, H.-C.; Lee, W.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 9 | 9 | |
2012 | Obstacle-avoiding free-assignment routing for flip-chip designs | Lee, P.-W.; Lee, H.-C.; Ho, Y.-K.; Chang, Y.-W.; Chang, C.-F.; Lin, I.-J.; Shen, C.-F.; YAO-WEN CHANG | Design Automation Conference | 2 | 0 | |
2019 | Obstacle-aware group-based length-matching routing for pre-assignment area-I/O flip-chip designs | Chang, Y.-H.; Wen, H.-T.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 3 | 0 | |
2014 | Overlay-Aware detailed routing for self-Aligned double patterning lithography using the cut process | Liu, I.-J.; Fang, S.-Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 25 | 0 | |
2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, T.-C.; Pan, S.-R.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | | |
2002 | Performance-driven placement for dynamically reconfigurable FPGAs | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
2020 | Phosphoproteome Analysis Reveals Dynamic Heat Shock Protein 27 Phosphorylation in Tanshinone IIA-Induced Cell Death | Yin, C.-F.; Kao, S.-C.; CHIA-LANG HSU ; Chang, Y.-W.; Cheung, C.H.Y.; Huang, H.-C.; Juan, H.-F. | Journal of Proteome Research | 10 | 8 | |
2014 | Photothermal optical coherence tomography based on the localized surface plasmon resonance of Au nanoring | Chi, T.-T.; Tu, Y.-C.; Li, M.-J.; Chu, C.-K.; Chang, Y.-W.; Yu, C.-K.; Kiang, Y.-W.; CHIH-CHUNG YANG ; YEAN-WOEI KIANG | Optics Express | 14 | 13 | |
2006 | Physical design for System-On-a-Chip | Chang, Y.-W.; Chen, T.-C.; Chen, H.-Y.; YAO-WEN CHANG | Essential Issues in SOC Design: Designing Complex Systems-on-Chip | 1 | 0 | |
2004 | Placement with alignment and performance constraints using the B*-tree representation | Wu, M.-C.; Chang, Y.-W.; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 15 | 0 | |
2009 | Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs | Lee, W.-P.; Marculescu, D.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 10 | 0 | |
2007 | Power/ground network and floorplan cosynthesis for fast design convergence | Liu, C.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 19 | 13 | |
2016 | Precise optical surface profilometry using innovative chromatic differential confocal microscopy | Chen, L.-C.; Nguyen, D.T.; Chang, Y.-W.; LIANG-CHIA CHEN | Optics Letters | | | |
2010 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | 9 | |
2008 | Predictive formulae for OPC with applications to lithography-friendly routing | Chen, T.-C.; Liao, G.-W.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |
2011 | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs | Chuang, Y.-L.; Lin, H.-T.; Ho, T.-Y.; Chang, Y.-W.; Marculescu, D.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 7 | 0 | |
2011 | Proceedings of the International Symposium on Physical Design: Foreword | Chang, Y.-W.; Hu, J.; YAO-WEN CHANG | International Symposium on Physical Design | 0 | | |
2016 | Provably good max-min-m-neighbor-TSP-based subfield scheduling for electron-beam photomask fabrication | Lin, Z.-W.; Fang, S.-Y.; Chang, Y.-W. ; Rao, W.-C.; CHIEH-HSIUNG KUAN ; YAO-WEN CHANG | 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 | 1 | 0 | |
2011 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 3 | 1 | |
2010 | Pulsed-latch aware placement for timing-integrity optimization | Chuang, Y.-L.; Kim, S.; Shin, Y.; Chang, Y.-W.; YAO-WEN CHANG | Design Automation Conference | 20 | 0 | |