Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
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2006 | A 0.7-2-GHz self-calibrated multiphase delay-locked loop | Hsiang-Hui Chang; Jung-Yu Chang; Chun-Yi Kuo; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 47 | 37 | |
2002 | A 0.8 V switched-opamp bandpass ΔΣ modulator using a two-path architecture | Hsiang-Hui Chang; Shang-Ping Chen; Kuang-Wei Cheng; SHEN-IUAN LIU | 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings | 2 | 0 | |
2005 | A calibrated pulse generator for impulse-radio UWB applications | Che-Fu Liang; Shih-Tsai Liu; Hsiang-Hui Chang; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits | 22 | ||
2003 | A fast locking and low jitter delay-locked loop using DHDL | Hsiang-Hui Chang; Jyh-Woei Lin; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 12 | ||
2003 | A Low Jitter and Precise Multiphase Delay-Locked Loop Using Shifted Averaging VCDL | Hsiang-Hui Chang; Chih-Hao Sun; SHEN-IUAN LIU | ISSCC 2003 | |||
2003 | A Shifted-Averaging VCO with Precise Multiphase Outputs and Low Jitter Operation | Hsiang-Hui Chang; Shang-Ping Chen; SHEN-IUAN LIU | 29th European Solid-State Circuits Conference | |||
2003 | A sub-1V fourth-order bandpass delta-sigma modulator | Hsiang-Hui Chang; Chien-Hung Kuo; Ming-Huang Liu; SHEN-IUAN LIU | Journal of Analog Integrated Circuits and Signal Processings | 0 | ||
2002 | A wide-range delay-locked loop with a fixed latency of one clock cycle | Hsiang-Hui Chang; Jyh-Woei Lin; Ching-Yuan Yang; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 112 | ||
2003 | An 800Mb/s tracking clock recovery receiver for the IEEE P1394a serial bus | Hsiang-Hui Chang; Giang-Kaai Dehng; SHEN-IUAN LIU | Bulletin of the College of Engineering, National Taiwan University | |||
2001 | CMOS Magnetic to Digital Converter Using Oversampling ModulatorCMOS Magnetic to Digital Converter Using Oversampling Modulator | Shr-Lung Chen; Hsiang-Hui Chang; Kun-Hsien Li; SHEN-IUAN LIU | 12th VLSI Design/CAD Symposium | |||
2004 | Low jitter and multi-rate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection | Hsiang-Hui Chang; Rong-Jyi Yang; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 12 |