公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2015 | A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. | Lin, Ye-Jyun; Yang, Chia-Lin; Li, Hsiang-Pang; CHIA-LIN YANG | IEEE Non-Volatile Memory System and Applications Symposium, NVMSA 2015, Hong Kong, China, August 19-21, 2015 | 14 | 0 | |
2015 | System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach | Lin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; CHIA-LIN YANG ; CHIH-WEN HSUEH | Acm Transactions on Embedded Computing Systems | 4 | 3 | |
2008 | Tunablevp: a tunable virtual platform for easy soc design space exploration | CHIA-LIN YANG ; Lin, Ye-Jyun; Chen, Yi-Jung; Huang, Chin-Chie; Lin, Tzu-Ching; Chi, Jaw-Wei; CHIA-LIN YANG | 2008 International SoC Design Conference, ISOCC 2008 | | | |
2015 | 系統層級智慧型個人裝置記憶體與儲存子系統效能功耗最佳化 | 林業峻; Lin, Ye-Jyun | | | | |