公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
1987 | Gate Drive for GTO Devices | S. Chin; D. Y. Chen; DAN CHEN | IEEE Industry Applications Society Annual Meeting | | | |
2023 | A Gate Driver IC for GaN-Based Synchronous Buck Converter with A Double-Sided Adaptive Dead- Time Generator | Thuc, Giao Huu; CHING-JAN CHEN | Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC | 0 | 0 | |
2003 | Gate leakage suppression and contact engineering in nitride heterostructures | YUH-RENN WU ; Singh, M; Singh, J | Journal of Applied Physics | | | |
2004 | Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate | J. B. Kuo; C. H. Hsu; C. P. Yang; JAMES-B KUO | IEEE Conference on Electron Devices and Solid-State Circuits | 3 | 0 | |
2004 | Gate Misalignment Effects of DG SOI NMOS Devices | JAMES-B KUO | VLSI/CAD Conference | | | |
2019 | Gate Oxide Local Thinning Mechanism Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor | C.F.Yang; P.J.Chen; W.C.Chen; K.W.Lin; J.G.Hwu; JENN-GWO HWU | IEEE Transactions on Electron Devices | 5 | 5 | |
2019 | Gate Oxide Local Thinning Mechanism-Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor | Yang, C.-F.; Chen, B.-J.; Chen, W.-C.; Lin, K.-W.; JENN-GWO HWU | IEEE Transactions on Electron Devices | | | |
2010 | Gate oxide wear out using novel polysilazane-base inorganic as nano-scaling shallow trench filling | Ho, Ching Yuan; Shih, Kai-Yao; He, Jr Hau | Microelectronic Engineering | 1 | 1 | |
2010 | Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect | H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO | Microelectronics Reliability | 5 | 6 | |
2009 | Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect | H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO | International Electron Devices Materials Symposium | | | |
2008 | Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor | Liao, M.H.; Liu, C.W.; Yeh, L.; Lee, T.-L.; CHEE-WEE LIU ; MING-HAN LIAO | Applied Physics Letters | 13 | 11 | |
2014 | Gate-all-around Ge FETs | CHEE-WEE LIU ; Liu, C.W.; Chen, Y.-T.; Hsu, S.-H.; CHEE-WEE LIU | ECS Transactions | | | |
2014 | Gate-bias stress stability of P-type SnO thin-film transistors fabricated by RF-sputtering | Chiu, I.-C.; Cheng, I.-C.; I-CHUN CHENG | IEEE Electron Device Letters | 63 | 63 | |
2019 | Gate-defined quantum dots in Ge/SiGe quantum wells as a platform for spin qubits | Hardy, W.J.; Su, Y.-H.; Chuang, Y.; Maurer, L.N.; Brickson, M.; Baczewski, A.; JIUN-YUN LI ; Lu, T.-M.; Luhman, D.R. | ECS Transactions | 2 | 0 | |
2006 | Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology | B. Chung; J. B. Kuo; JAMES-B KUO | ISCAS | 0 | 0 | |
2006 | Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique | B. Chung; J. B. Kuo; JAMES-B KUO | PATMOS | | | |
2008 | Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application | B. Chung; JAMES-B KUO | Integration, the VLSI Journal | 10 | 10 | |
2008 | Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications | R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO | ICSICT | 1 | 0 | |
2005 | Gate-Misalignment Related Capacitance Behavior of a 100nm DG SOI MOS Devices with N+/p+ Top/Bottom Gate | J. B. KUo; C. H. Hsu; C. P. Yang; JAMES-B KUO | HKEDSSC | | | |
2014 | Gate-tunable Kondo resistivity and dephasing rate in graphene studied by numerical renormalization group calculations | GUANG-YU GUO | Physical Review B - Condensed Matter and Materials Physics | 11 | 10 | |