An IR-drop guided test pattern generation technique
Journal
International Symposium on VLSI Design, Automation and Test
Date Issued
2016
Author(s)
Abstract
The high switching activity during at-speed scan testing has been known to cause yield loss because the incurred IR-drop can result in excessive performance degradation and cause a good device to fail. In this work, we propose an IR-drop guided test pattern generation technique that tunes the switching activity distribution to match the user-specified one. Simulation results show significant improvement (96% cost reduction in average) in matching IR-drop profiles with minor test inflation.
Type
conference paper