On-chip random jitter testing using low tap-count coarse delay lines
Resource
Journal of Electronic Testing 22 (4-6): 387-398
Journal
Journal of Electronic Testing: Theory and Applications (JETTA)
Journal Volume
22
Journal Issue
4-6
Pages
387 - 398
Date Issued
2006-12
Author(s)
Abstract
An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations. © Springer Science + Business Media, LLC 2006.
Subjects
Analog/mixed-signal testing; Design-for-test; Jitter measurement; Random jitter
Other Subjects
Computer simulation; Design for testability; Electric delay lines; Microprocessor chips; Probability; Probability density function; Analog/mixed signal testing; Delay line value deviations; Jitter measurement; Random jitters; Jitter
Type
journal article
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