A built-in characterization technique for 1-bit/stage pipelined ADC
Journal
Proceedings of the Asian Test Symposium
Pages
284-289
Date Issued
2012
Author(s)
Abstract
In this paper, we present, for the 1-bit/stage pipelined ADC, a self-characterization technique that quantifies the per-stage capacitor ratio and comparator offset - the two main nonlinearity sources. In the proposed loop test, two adjacent pipelined stages are reconfigured to form a loop. Then, DC test stimuli are applied. The capacitor ratio and comparator offset of the stage under test are derived from the recorded output sequences. Numerical simulations are performed to validate the proposed technique.
Type
conference paper