https://scholars.lib.ntu.edu.tw/handle/123456789/148943
標題: | Low voltage CMOS four-quadrant multiplier | 作者: | SHEN-IUAN LIU | 關鍵字: | CMOS integrated circuits; Multiplying circuits | 公開日期: | 十二月-1994 | 卷: | 30 | 期: | 25 | 起(迄)頁: | 2125-2126 | 來源出版物: | Electronics Letters | 摘要: | A new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5V the differential linear range is over ±0.8V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6V, The simulated -3dB bandwidth of this multiplier is about 12MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications. © 1994, IEE. All rights reserved. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/2007041910042620 https://www.scopus.com/inward/record.uri?eid=2-s2.0-0028768768&doi=10.1049%2fel%3a19941427&partnerID=40&md5=9ce3271e55884ed41f169ed52986323b |
ISSN: | 00135194 | DOI: | 10.1049/el:19941427 | SDG/關鍵字: | Buffer circuits; CMOS integrated circuits; Computer simulation; Electric current control; Frequency stability; Gain control; Harmonic analysis; Integrated circuit layout; Transistors; Triodes; VLSI circuits; Voltage control; Four quadrant multiplier; Harmonic distortion; Software package SPICE; Multiplying circuits |
顯示於: | 電機工程學系 |
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00350154.pdf | 200.11 kB | Adobe PDF | 檢視/開啟 |
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