https://scholars.lib.ntu.edu.tw/handle/123456789/149699
Title: | Test Time Reduction in Scan Designed Circuits | Authors: | Lai, W. Kung, C. 林呈祥 Lin, Chen-Shang |
Issue Date: | 1993 | Start page/Pages: | - | Source: | EDAC-EUROASIC | URI: | http://ntur.lib.ntu.edu.tw//handle/246246/121613 |
Appears in Collections: | 電機工程學系 |
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