https://scholars.lib.ntu.edu.tw/handle/123456789/154734
標題: | Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme | 作者: | Lin, Jai-Ming YAO-WEN CHANG Lin, Shih-Ping |
關鍵字: | Floor planning; Layout; Physical design; Placement; VLSI design | 公開日期: | 2003 | 卷: | 11 | 期: | 4 | 起(迄)頁: | 679-686 | 來源出版物: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 摘要: | Floorplanning/placement allocates a set of modules into a chip so that no two modules overlap and some specified objective is optimized. To facilitate floorplanning/placement, we need to develop an efficient and effective representation to model the geometric relationship among modules. In this paper, we present a P-admissible representation, called corner sequence (CS), for non-slicing floorplans. CS consists of two tuples that denote the packing sequence of modules and the corners to which the modules are placed. CS is very effective and simple for implementation. Also, it supports incremental update during packing. In particular, it induces a generic worst case linear-time packing scheme that can also be applied to other representations. Experimental results show that CS achieves very promising results for a set of commonly used MCNC benchmark circuits. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/141380 http://ntur.lib.ntu.edu.tw/bitstream/246246/141380/1/17.pdf https://www.scopus.com/inward/record.uri?eid=2-s2.0-0141750617&doi=10.1109%2fTVLSI.2003.816137&partnerID=40&md5=70eee4a7116d80cd935a89fff8de7786 |
ISSN: | 10638210 | DOI: | 10.1109/TVLSI.2003.816137 | SDG/關鍵字: | Graph theory; Mathematical models; Planning; Polynomials; Linear-time packing schemes; VLSI circuits |
顯示於: | 電機工程學系 |
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