https://scholars.lib.ntu.edu.tw/handle/123456789/173876
標題: | 總計畫:具有內建自我測試功能之5GHz超低功率無線通訊系統之研製 子計畫二:超低功率類比前端處理器 | 作者: | 李泰成 | 關鍵字: | frequency synthesizer;phase-locked loop;analog correlator;analog-to-digital converter | 公開日期: | 31-七月-2005 | 出版社: | 臺北市:國立臺灣大學電子工程學研究所 | 摘要: | This report summarizes the simulation and experimental results of the subproject II – An ultra low-power analog front-end processor, including frequency synthesizer, correlator, and A/D converter. The frequency synthesizer consists of a phase/ frequency detector (PFD), a charge pump (CP) with analog adaptive BW control, a second- order loop filter, a voltage control oscillator (VCO), and a frequency divider. The VCO is implemented using the hollow-coil spiral inductor, and varactor to control the wanted frequency. The frequency divider adopts pulse-swallow architecture and use sourcecoupled logic (SCL) structure to reduce the switching noise; The analog correlator composes a single differential sampling cell, the circuits of clock generation and control signalsBthe A/D converter composes preamplifiers, comparators and double interpolation circuits. In the first and the second year, system simulations would be optimized, based on lower-power architecture and circuit design techniques for low-power analog signal processors. The direct conversion architecture in subproject I creates DC-offset problem, thereby demanding a low-power DC-offset canceller/corrector to relax the design of the analog correlator. So far, the frequency synthesizer and correlator have been designed, fabricated and measured. Additionally, the ADC have been simulated and is under fabrication and optimized for the low-power application. The overall system requirements are also determined by the aid of the commercial information. The circuit implementation of each building block is on going. |
URI: | http://ntur.lib.ntu.edu.tw//handle/246246/20059 | 其他識別: | 932220E002010 | Rights: | 國立臺灣大學電子工程學研究所 |
顯示於: | 電子工程學研究所 |
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932220E002010.pdf | 1.09 MB | Adobe PDF | 檢視/開啟 |
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