https://scholars.lib.ntu.edu.tw/handle/123456789/292079
標題: | Scalable module-based architecture for MPEG-4 BMA motion estimation | 作者: | Hsu, M.-Y. Chang, H.-C. Wang, Y.-C. LIANG-GEE CHEN |
公開日期: | 2001 | 卷: | 2 | 起(迄)頁: | 245-248 | 來源出版物: | ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings | 會議論文: | 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 | 摘要: | In this paper, we present a scalable module-based architecture for block matching motion estimation algorithm of MPEG-4. The basic module comprises one set of processing elements based on one-dimensional systolic array architecture. To support various applications, modules of processing elements can be configured to form the processing element array to meet the requirements, such as variable block size, search range and computation power. And this proposed architecture has the advantage of few I/O port counts. Based on eliminating unnecessary signal transitions in the processing element, power dissipation of datapath can be reduced to about half without decreasing the picture quality. © 2001 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0035016247&doi=10.1109%2fISCAS.2001.921053&partnerID=40&md5=72d91e7e6228777d31b79ee1040e5228 http://scholars.lib.ntu.edu.tw/handle/123456789/292079 |
DOI: | 10.1109/ISCAS.2001.921053 | SDG/關鍵字: | Block matching motion estimation; Computation power; Picture quality; Processing elements; Proposed architectures; Signal transition; Systolic array architecture; Variable block size; Motion Picture Experts Group standards; Computer architecture; Image quality; Motion estimation; Switching circuits; Systolic arrays; Motion estimation; Image compression; Polygon matching; Power dissipation |
顯示於: | 電機工程學系 |
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00921053.pdf | 365.09 kB | Adobe PDF | 檢視/開啟 |
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