https://scholars.lib.ntu.edu.tw/handle/123456789/301454
標題: | Concurrent Error-Detectable Butterfly Chip for Real-Time FFT Processing Through Time Redundancy | 作者: | Chen, T.-H. LIANG-GEE CHEN |
公開日期: | 1993 | 卷: | 28 | 期: | 5 | 起(迄)頁: | 537-547 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | This paper presents a chip design of a fast Fourier transform (FFT) butterfly module with a novel concurrent error detection (CED) technique. It is a time-redundant realization based on the direct complex computation approach. By symmetric and exchanging designing strategy, the recomputation step can be performed by interleaving the real part and imaginary part circuits in a complex function. It leads to less hardware overhead of about 7/(4n + 8) where n is the word length, and the capability of error detection is still as robust as the duplicated module technique. The CED butterfly is designed with 1.2-μm CMOS technology by using the structural silicon compiler. Theoretical analysis and experimental results are presented. It is shown that this design is very attractive in the real-time high-reliability DSP system. Its regular structure reveals that the proposed algorithm and architecture are easy to implement on VLSI or WSI. © 1993 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-0027592819&doi=10.1109%2f4.229402&partnerID=40&md5=e8c1e22c7e4aa435469fff8bcbe719af http://scholars.lib.ntu.edu.tw/handle/123456789/301454 |
ISSN: | 00189200 | DOI: | 10.1109/4.229402 | SDG/關鍵字: | Algorithms; CMOS integrated circuits; Digital signal processing; Fast Fourier transforms; Program compilers; Semiconducting silicon; Concurrent error-detectable butterfly chip; Real-time FFT processing; Recomputation step; Time redundancy; VLSI circuits |
顯示於: | 電機工程學系 |
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