https://scholars.lib.ntu.edu.tw/handle/123456789/313902
標題: | Multiple-lifting Scheme: Memory-efficient VLSI implementation for line-based 2-D DWT | 作者: | Cheng, C.-C. Huang, C.-T. Tseng, P.-C. Pan, C.-H. LIANG-GEE CHEN |
公開日期: | 2005 | 起(迄)頁: | 5190-5193 | 來源出版物: | Proceedings - IEEE International Symposium on Circuits and Systems | 會議論文: | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 | 摘要: | In this paper, a memory-efficient VLSI implementation for line-based 2-D DWT, named multiple-lifting scheme, is proposed.Memory bandwidth and memory size dominate the cost of 2-D DWT and are highly related to the total power and area of 2-D DWT VLSI implementation, respectively. The proposed multiple-lifting scheme can reduce not only the average memory bandwidth but about 50% area of line buffer in 2-D DWT module. The corresponding data scan, M-scan, is proposed to achieve the multiple-lifting scheme and eliminate the data buffer as well. © 2005 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-33947638761&doi=10.1109%2fISCAS.2005.1465804&partnerID=40&md5=eee8316f833e5874df472f0386952e2f http://scholars.lib.ntu.edu.tw/handle/123456789/313902 |
ISSN: | 02714310 | DOI: | 10.1109/ISCAS.2005.1465804 | SDG/關鍵字: | Data buffers; Lifting schemes; Memory bandwidths; Memory size; Total power; VLSI implementation; Discrete wavelet transforms |
顯示於: | 電機工程學系 |
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