https://scholars.lib.ntu.edu.tw/handle/123456789/332261
標題: | 2.8 to 67.2mW low-power and power-aware H.264 encoder for mobile applications | 作者: | Chen, T.-C. Chen, Y.-H. Tsai, C.-Y. Tsai, S.-F. SHAO-YI CHIEN LIANG-GEE CHEN |
公開日期: | 2007 | 起(迄)頁: | 222-223 | 來源出版物: | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | 會議論文: | 2007 Symposium on VLSI Circuits, VLSIC | 摘要: | A 2.8 to 67.2mW H.264 encoder is implemented on a 12.8mm2 die with 0.18μm CMOS technology. The proposed parallel architectures along with fast algorithms and data reuse schemes enable 77.9% power savings. The power awareness is provided through a flexible system hierarchy that supports content-aware algorithms and module-wise gated clock. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-39749116345&doi=10.1109%2fVLSIC.2007.4342727&partnerID=40&md5=2f852b5b09db7780bb51cfb8f9dd8849 http://scholars.lib.ntu.edu.tw/handle/123456789/332261 |
DOI: | 10.1109/VLSIC.2007.4342727 | SDG/關鍵字: | Algorithms; Data processing; Reusability; Data reuse schemes; Gated clock; Mobile applications; System hierarchy; CMOS integrated circuits |
顯示於: | 電子工程學研究所 |
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