https://scholars.lib.ntu.edu.tw/handle/123456789/427676
標題: | Routing-Based Traffic Migration and Buffer Allocation Schemes for Three-Dimensional Network-on-Chip Systems with Thermal Limit | 作者: | Chih-Hao Chao Kun-Chih Chen An-Yeu (Andy) Wu AN-YEU(ANDY) WU |
公開日期: | 2013 | 卷: | 21 | 期: | 11 | 起(迄)頁: | 82-91 | 來源出版物: | IEEE Transactions on Very Large Scale Integration Systems (TVLSI) | 摘要: | The 3-D network-on-chip (NoC) router is a major source of thermal hotspots, limiting the performance gain of 3-D integration. Due to the varying cooling efficiency of different silicon layers in 3-D NoC, the optimal criteria of traditional load balancing design (LBD) scheme and temperature balancing design (TBD) scheme may not be satisfied. To analyze the tradeoff between performance and temperature, we provide a new analytical model. The model shows that the LBD scheme and the TBD scheme can be considered as two corner cases in the design space, and design cases can be categorized by comparing the bandwidth bound and the thermal-limited bound. To find the optimal design criteria between the LBD and the TBD schemes in 3-D NoC, we propose a new routing-based traffic migration, vertical-downward lateral-adaptive proactive routing (VDLAPR), and buffer allocation methods, vertical buffer allocation (VBA). The VDLAPR algorithm enables to tradeoff between the LBD and the TBD schemes. The proposed VBA method mitigates the traffic congestion caused by traffic migration. To reach the optimal configuration, we propose a systematic design flow, which assists in finding the best design parameters in the expanded space between LBD and TBD. Based on the traffic-thermal co-simulation experiments, the achievable throughput can be improved from 2.7% to 45.2% using the proposed design scheme. © 2013 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/427676 | DOI: | 10.1109/TVLSI.2012.2227852 | SDG/關鍵字: | 3-D NoC; Achievable throughputs; Buffer allocation; Cooling efficiency; downward routing; Network on chip; Network-on-chip systems; Systematic designs; Design; Servers; Traffic congestion; VLSI circuits; Routers |
顯示於: | 電機工程學系 |
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