https://scholars.lib.ntu.edu.tw/handle/123456789/427695
Title: | Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel | Authors: | Fan-Min Li Cheng-Hung Lin AN-YEU(ANDY) WU 吳安宇 |
Keywords: | Convolutional code; Forward-error-correction code; Log-MAP; Maximum a-posteriori probability; Reconfigurable FEC architecture; Turbo code; Viterbi algorithm | Issue Date: | 2008 | Journal Volume: | 16 | Journal Issue: | 10 | Start page/Pages: | 2228-2239 | Source: | Transactions on Very Large Scale Integration (VLSI) Systems | Abstract: | To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo decoder is proposed. In this paper, we systematically analyze the timing charts of both the Viterbi algorithm and the MAP algorithm. Then, three techniques, including Distribution, Pointer, and Parallel schemes, are introduced; they can be used as flexible tools in timing-chart analysis to either reduce memory size or to increase throughput rate. Furthermore, we propose a tile-based methodology to analyze the key features of timing charts, such as computing/memory units and hardware utilization. On the basis of the timing analysis, we developed a VA/MAP timing chart that has three modes (VA mode, MAP mode, and concurrent VA/MAP mode) by complementing the idle time of both VA and MAP decoding procedures. The new combined timing analysis helps us for constructing a unified component decoder with near 100% utilization rate of the processing element (PE) in both VA/MAP decoding functions. According to the triple-mode VA/MAP timing chart, we construct a triple-mode FEC kernel that can perform both Convolutional/Turbo decoding functions seamlessly for different communication systems. By integrating the FEC kernel with different size of memory, we can construct four types of FEC decoders for different application scenarios, such as 1) standalone Convolutional decoder (VA mode); 2) standalone Turbo decoder (MAP mode); 3) dualmode Convolutional/Turbo decoder (VA mode and MAP mode); and 4) triple-mode Convolutional/Turbo decoder (VA mode, MAP mode, and concurrent VA/MAP mode). Finally, a prototyping FEC kernel processor that is compliant to 3GPP standard is verified in TSMC 0.18-m CMOS process in the type of triple-mode FEC decoder. © 2008 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/427695 https://www.scopus.com/inward/record.uri?eid=2-s2.0-52649133391&doi=10.1109%2fTVLSI.2008.2000514&partnerID=40&md5=76cf47d1baa7d60f29741054756008de |
ISSN: | 10638210 | DOI: | 10.1109/tvlsi.2008.2000514 | SDG/Keyword: | Codes (standards); Codes (symbols); Communication systems; Conformal mapping; Convolution; Convolutional codes; Data storage equipment; Error correction; Forward error correction; Graphic methods; Maps; Standards; Time measurement; Turbo codes; Video streaming; Viterbi algorithm; 3GPP standards; Application scenarios; Chart analyses; CMOS processing; Convolutional code; Different sizes; FEC decoders; Flexible tools; Forward-error-correction code; Hardware utilization; Idle time; Log-MAP; MAP algorithms; MAP decoding; Maximum a-posteriori probability; Memory size; Processing-element; Prototype designs; Prototyping; Reconfigurable FEC architecture; Throughput rates; Timing Analysis; Turbo code; Turbo decoders; Viterbi; Decoding |
Appears in Collections: | 電機工程學系 |
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