An at-speed self-testable technique for the high speed domino adder
Journal
Proceedings of the Custom Integrated Circuits Conference
Date Issued
2011
Author(s)
Abstract
An at-speed self-testable technique is proposed for the high speed domino adder. We apply pseudo-exhaustive testing so that all testable faults in the 64-bit adder are detected by just 23K patterns. The adder latency is accurately measured by the programmable-skew clock generated from delay-locked loop (DLL). The proposed technique is validated on a 6.4GHz 64-bit domino adder with 181ps latency in 90nm CMOS technology. This on-chip technique is very useful for at-speed testing and speed binning of high performance CPU.
SDGs
Type
conference paper