https://scholars.lib.ntu.edu.tw/handle/123456789/501348
標題: | Testability Measures Considering Circuit Reconvergence to Reduce ATPG Runtime | 作者: | Chen, K.-H. Chen, C.-Y. JIUN-LANG HUANG |
關鍵字: | ATPG; backtrack; reconvergence; Testability | 公開日期: | 2019 | 來源出版物: | Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 | 會議論文: | 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 | 摘要: | Reconvergence has been recognized as the main reason for ATPG backtrack. It induces not only more, but also prolonged backtracks and causes more severe performance degradation than expected. In this paper, we propose a reconvergence-aware testability measure to better guide the ATPG justification process. Experiment results show that the proposed method significantly decreases the ATPG runtime, especially for circuits with deep logic level, by up to 76%. © 2019 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/501348 https://www.scopus.com/inward/record.uri?eid=2-s2.0-85067547684&doi=10.1109%2fDDECS.2019.8724660&partnerID=40&md5=266cc7fe12eadf91c63c721d625ba838 |
DOI: | 10.1109/DDECS.2019.8724660 | SDG/關鍵字: | ATPG; backtrack; Justification process; Logic levels; Performance degradation; Re convergences; Testability; Testability measures; Timing circuits |
顯示於: | 電機工程學系 |
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