On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs
Journal
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Pages
143-151
Date Issued
2008
Author(s)
Wu, S.
Wang, L.-T.
Jiang, Z.
Song, J.
Sheu, B.
Wen, X.
Hsiao, M.S.
Li, J.C.-M.
Huang, J.-L.
Type
conference paper