On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs
Journal
Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Pages
143-151
Date Issued
2008
Author(s)
Wu, S.
Wang, L.-T.
Jiang, Z.
Song, J.
Sheu, B.
Wen, X.
Hsiao, M.S.
Li, J.C.-M.
Huang, J.-L.
Abstract
This paper presents a hybrid automatic test pattern generation (ATPG) technique using the staggered single-capture scheme followed by the one-hot single-capture scheme for detecting structural faults, which are neither timing-dependent nor sequence-dependent in a scan design. Structural faults are also called combinational faults or DC faults, such as stuck-at faults and bridging faults. Typically, the one-hot scheme achieves near maximum fault coverage, takes shorter ATPG run time, but produces a large pattern count, whereas the staggered scheme produces smaller pattern count but needs long ATPG run time and may suffer from some fault coverage loss. The proposed hybrid technique is intended to optimize fault coverage with respect to the one-hot scheme by exploring trade-offs between pattern count and ATPG run time of multimillion-gate scan designs. Experimental results show that the proposed hybrid technique can achieve higher fault coverage and up to 4X smaller pattern count than the one-hot scheme.
Type
conference paper