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College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction
Details
A Multi-Fault Dynamic Compaction Technique for Test Pattern Count Reduction
Journal
Proceedings - International SoC Design Conference 2018, ISOCC 2018
Pages
9-10
Date Issued
2019
Author(s)
Li, B.-Y.
JIUN-LANG HUANG
DOI
10.1109/ISOCC.2018.8649901
URI
https://scholars.lib.ntu.edu.tw/handle/123456789/501356
URL
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85063190588&doi=10.1109%2fISOCC.2018.8649901&partnerID=40&md5=22c307478291321cbbca28c210af22d4
SDGs
[SDGs]SDG9
Type
conference paper