https://scholars.lib.ntu.edu.tw/handle/123456789/580640
標題: | Self-Heating Induced Interchannel Vt Difference of Vertically Stacked Si Nanosheet Gate-All-Around MOSFETs | 作者: | Chung C.-C Ye H.-Y Lin H.H Wan W.K Yang M.-T CHEE-WEE LIU |
關鍵字: | Nanosheets; Temperature distribution; Threshold voltage; Channel number; Gate-all-around; Input power; Interface trap density; Junction temperatures; MOSFETs; Self-heating; Temperature dependence; MOSFET devices | 公開日期: | 2019 | 卷: | 40 | 期: | 12 | 起(迄)頁: | 1913-1916 | 來源出版物: | IEEE Electron Device Letters | 摘要: | The natural asymmetry of the vertically stacked channels results in the junction temperature difference in nanosheet channels which is dependent on pitch, nanosheet width, channel number, and input power. The Vt difference induced by the self-heating becomes worse with the process imperfections, such as the interface trap density. PFET has higher Vt difference due to the higher thermal resistance and stronger temperature dependence of Vt than nFET (22mV vs 6.5mV for 15nm pitch, 35nm nanosheet width, 3 channels, and DC input). The Vt difference increases with the increasing channel number and nanosheet width. ? 1980-2012 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85076280349&doi=10.1109%2fLED.2019.2945474&partnerID=40&md5=cb5849cec1060f2f8d9178bbc4844e7d https://scholars.lib.ntu.edu.tw/handle/123456789/580640 |
ISSN: | 07413106 | DOI: | 10.1109/LED.2019.2945474 |
顯示於: | 電機工程學系 |
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