https://scholars.lib.ntu.edu.tw/handle/123456789/580985
標題: | Time multiplexing via circuit folding | 作者: | Chien P.-C JIE-HONG JIANG |
關鍵字: | Bandwidth; Computer aided design; Economic and social effects; Flip flop circuits; Table lookup; Timing circuits; Bandwidth bottlenecks; Circuit partitioning; Functional circuits; Functional methods; Look up table; Physical design; Structural methods; Time multiplexing; Time division multiplexing | 公開日期: | 2020 | 卷: | 2020-July | 來源出版物: | Proceedings - Design Automation Conference | 摘要: | Time multiplexing is an important technique to overcome the bandwidth bottleneck of limited input-output pins in FPGAs. Most prior work tackles the problem from a physical design standpoint to minimize the number of cut nets or Time Division Multiplexing (TDM) ratio through circuit partitioning or routing. In this work, we formulate a new orthogonal approach at the logic level to achieve time multiplexing through structural and functional circuit folding. The new formulation provides a smooth trade-off between bandwidth and throughput. Experiments show the effectiveness of the structural method and improved optimality of the functional method on look-up-table and flip-flop usage. ? 2020 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85093982417&doi=10.1109%2fDAC18072.2020.9218552&partnerID=40&md5=6a24117451238169070b2c48fc27b1a6 https://scholars.lib.ntu.edu.tw/handle/123456789/580985 |
ISSN: | 0738100X | DOI: | 10.1109/DAC18072.2020.9218552 |
顯示於: | 電機工程學系 |
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