https://scholars.lib.ntu.edu.tw/handle/123456789/630955
標題: | Fault Modeling and Testing of Spiking Neural Network Chips | 作者: | Hsieh, Yi Zhan Tseng, Hsiao Yin Chiu, I. Wei CHIEN-MO LI |
公開日期: | 1-一月-2021 | 來源出版物: | Proceedings - 2021 IEEE International Test Conference in Asia, ITC-Asia 2021 | 摘要: | Spiking neural network (SNN) is a very promising low-power neural network that can be implemented in asynchronous circuits. However, it is hard to test SNN chips since they are inherently probabilistic and fault tolerant. So far, there is no good fault model and test methodology suitable for SNN chips. In this paper, we propose seven behavior fault models for SNN based on the function of neurons and synapses. We also propose a test methodology, which considers the output response as a distribution rather than specific values. The experiment results on a MNIST dataset show that although SNN is fault tolerant, two fault models are still critical for SNN chips. Given the digit recognition application, the accuracy of chips that passed our test is 88.90%, which is indistinguishable from that of good chips, even in the effects of random seeds. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/630955 | ISBN: | 9781665413343 | DOI: | 10.1109/ITC-Asia53059.2021.9808431 |
顯示於: | 電機工程學系 |
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