https://scholars.lib.ntu.edu.tw/handle/123456789/632358
標題: | A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator | 作者: | Chang J.-R SHEN-IUAN LIU |
關鍵字: | Fast-locking; low pass filter; phase error compensator; phase-locked loop; resettable divider | 公開日期: | 2022 | 卷: | 69 | 期: | 4 | 起(迄)頁: | 2026-2030 | 來源出版物: | IEEE Transactions on Circuits and Systems II: Express Briefs | 摘要: | A fast-locking phase-locked loop (PLL) using the proposed phase error compensator (PEC) is presented. The PEC compensates the accumulated phase error during the frequency acquisition process to enhance the settling time of this PLL. This PLL is fabricated in a 40-nm CMOS process. The output frequency of the PLL ranges from 2 to 3 GHz. When this PLL is switched from 2 GHz to 3 GHz, the measured settling time using the PEC is 0.6us which is around 30 reference clock cycles. The power consumption of the PLL is 4.6mW at 3 GHz for a supply of 1V. The integral root-mean-square jitter over 1 kHz to 100 MHz is 2.99ps. © 2004-2012 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85122277965&doi=10.1109%2fTCSII.2021.3138801&partnerID=40&md5=6c2e9261ab4cc75b9f37b3748c31f236 https://scholars.lib.ntu.edu.tw/handle/123456789/632358 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2021.3138801 | SDG/關鍵字: | Bandpass filters; Circuit oscillations; Clocks; Errors; Locks (fasteners); Oscillistors; Phase comparators; Phase locked loops; Variable frequency oscillators; Voltage dividers; Acquisition process; Charge-pump; Fast-locking; Frequency acquisition; Low-pass filters; Phase error; Phase error compensator; Phase-frequency detectors; Resettable divider.; Settling time; Low pass filters |
顯示於: | 電機工程學系 |
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