https://scholars.lib.ntu.edu.tw/handle/123456789/632485
標題: | Clock Design Methodology for Energy and Computation Efficient Bitcoin Mining Machines | 作者: | Lu C.-P HUI-RU JIANG Yang C.-W. |
關鍵字: | ai chips; bitcoin mining machines; blockchain; clock network synthesis; data flow; deep pipelines; near-threshold computing; secure hash algorithms | 公開日期: | 2022 | 起(迄)頁: | 13-20 | 來源出版物: | Proceedings of the International Symposium on Physical Design | 摘要: | Bitcoin mining machines become a new driving force to push the physical limitation of semiconductor process technology. Instead of peak performance, mining machines pursue energy and computation efficiency of implementing cryptographic hash functions. Therefore, the state-of-the-art ASIC design of mining machines adopts near-threshold computing, deep pipelines, and uni-directional data flow. According to these design properties, in this paper, we propose a novel clock reversing tree design methodology for bitcoin mining machines. In the clock reversing tree, the clock of global tree is fed from the last pipeline stage backward to the first one, and the clock latency difference between the local clock roots of two consecutive stages maintains a constant delay. The local tree of each stage is well balanced and keeps the same clock latency. The special clock topology naturally utilizes setup time slacks to gain hold time margins. Moreover, to alleviate the incurred on-chip variations due to near-threshold computing, we maximize the common clock path shared by flip-flops of each individual stage. Finally, we perform inverter pair swap to maintain duty cycle. Experimental results show that our methodology is promising for industrial bitcoin mining designs: Compared with two variation-aware clock network synthesis approaches widely used in modern ASIC designs, our approach can reduce up to 64% clock buffer/inverter usage, 12% clock power, decrease 99% hold time violating paths, and achieve 85% area saving for timing fixing. The proposed clock design methodology is general and applicable to blockchain and other ASICs with deep pipelines and strong data flow. © 2022 ACM. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85128594228&doi=10.1145%2f3505170.3506720&partnerID=40&md5=15898c32189ab0c8af9eef4d7db3416d https://scholars.lib.ntu.edu.tw/handle/123456789/632485 |
DOI: | 10.1145/3505170.3506720 | SDG/關鍵字: | Bitcoin; Clocks; Computational efficiency; Data transfer; Flip flop circuits; Forestry; Hash functions; Pipelines; Ai chip; Bitcoin mining machine; Block-chain; Clock network synthesis; Dataflow; Deep pipelines; Design Methodology; Mining machines; Near-Threshold Computing; Secure Hash Algorithm (); Blockchain |
顯示於: | 電機工程學系 |
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