First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles
Journal
Digest of Technical Papers - Symposium on VLSI Technology
Journal Volume
2023-June
ISBN
9784863488069
Date Issued
2023-01-01
Author(s)
Chen, Yu Rui
Liu, Yi Chun
Zhao, Zefu
Hsieh, Wan Hsuan
Lee, Jia Yang
Tu, Chien Te
Huang, Bo Wei
Wang, Jer Fu
Chueh, Shee Jier
Xing, Yifan
Chen, Guan Hua
Chou, Hung Chun
Woo, Dong Soo
Lee, M. H.
Abstract
The large memory window of 1.8V at the low write voltage of 2V is achieved by stacked two nanosheet (NS) gate-allaround (GAA) Ge0.98Si0.02 FeFETs with the channel phosphorus concentration larger than 1E18cm-3, enabling the erase of GAA FeFET. Isotropic wet etching was used in channel release process. Stacked two NSs have the advantages of reducing cell variation and 2X read current. The stable storage with data retention of > 1E4 seconds, linearly extrapolated 10 years, and high endurance > 1E11 cycles are also demonstrated. The thermal budget is as low as 400°C. The stacked NS architecture with high mobility channels makes FeFETs to be compatible with the 2nm node and beyond.
Type
conference paper