Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
---|---|---|---|---|---|---|
2003 | Simultaneous routing and buffering in floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | International Symposium on VLSI Technology, Systems, and Applications | 1 | 0 | |
2004 | Simultaneous routing and buffering in SOC floorplan design | Fang, J.P.; Tong, Y.-S.; SAO-JIE CHEN | IEE Proceedings: Computers and Digital Techniques | 5 | 5 |