公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2013 | A circular pipeline processing based deterministic parallel test pattern generator | K.-W. Yeh; J.-L. Huang; H.-J. Chao; L.-T. Wang; JIUN-LANG HUANG | International Test Conference | 9 | 0 | |
2009 | A Low Communication Overhead and Load Balanced Parallel ATPG with Improved Static Fault Partition Method | K.-W. Yeh; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | International Conference on Algorithms and Architectures for Parallel Processing | 10 | 0 | |
2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2015 | A static bidirectional learning technique to accelerate test pattern generation | J.-H. Pan; K.-W. Yeh; J.-L. Huang; JIUN-LANG HUANG | International SoC Design Conference | 0 | 0 |