第 1 到 66 筆結果,共 66 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2004 | A wideband analog correlator system for AMiBA | Li, C.-T.; Kubo, D.; Han, C.-C.; Chen, C.-C.; Chen, M.-T.; Lien, C.-H.; Wang, H.; Wei, R.-M.; Yang, C.-H.; Chiueh, T.-D.; Peterson, J.; Kesteven, M.; TZI-DAR CHIUEH ; CHIA-HSIANG YANG ; HUEI WANG | Proceedings of SPIE - The International Society for Optical Engineering | 18 | 0 | |
2 | 2020 | Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS | Chiueh, H.; Yang, C.-H.; Wen, C.H.-P.; Yang, C.-G.; Chien, P.-H.; Hung, C.-Y.; Chen, Y.-J.; Wang, Y.-P.; Chiu, C.-F.; Lin, J.; CHIA-HSIANG YANG | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | |||
3 | 2013 | Power and area reduction in multi-stage addition using operand segmentation | CHIA-HSIANG YANG ; Chan, C.-D.; Liu, W.-C.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 | |||
4 | 2018 | Performance of pre-production band 1 receiver for the Atacama Large Millimeter/submillimeter Array (ALMA) | Huang Y.-D.T; Morata O; Koch P.M; Kemper C; Hwang Y.-J; Chiong C.-C; Ho P.T.P; Chu Y.-H; Huang C.-D; Liu C.-T; Hsieh F.-C; Tseng Y.-H; CHIA-HSIANG YANG ; Tsay J.J; Chang T; Ho C.-T; Chiang P.-H; Chang C.-C; Jian S.-T; Hsu S.-P; Chien C; Iguchi S; Asayama S; Iono D; Gonzalez A; Effland J; Saini K; Pospieszalski M; Henke D; Yeung K; Finger R; Tapia V; Reyes N. | Proceedings of SPIE - The International Society for Optical Engineering | 5 | 0 | |
5 | 2019 | Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. | Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; CHIA-HSIANG YANG | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019 | |||
6 | 2018 | Massive MIMO detection VLSI design. | CHIA-HSIANG YANG | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 | |||
7 | 2020 | Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax | Wang Y.-P; Wen C.-C; Kao C.-C; Huang C.-J; Liu D.-Z; CHIA-HSIANG YANG | 2020 IEEE Global Communications Conference, GLOBECOM 2020 - Proceedings | |||
8 | 2017 | Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables | H.-T. Lin; Y.-C. Wu; P.-H. Hsieh; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | 1 | 0 | |
9 | 2020 | Improved design and in vivo animal tests of bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulation and neural action potential acquisition | Wang S.-H; Huang Y.-K; Chen C.-Y; Lee C.-F; Yang C.-H; Hung C.-C; Liu C.-H; Ker M.-D; CHIEN-HAO LIU ; CHIA-HSIANG YANG | 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 | 3 | 0 | |
10 | 2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. | Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming; CHIA-HSIANG YANG | Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012 | |||
11 | 2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection | CHIA-HSIANG YANG ; Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | 2012 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 | |||
12 | 2022 | Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression | Kao, Chen Chien; Hsieh, Yi Yen; Chen, Chao Hung; CHIA-HSIANG YANG | Midwest Symposium on Circuits and Systems | 1 | 0 | |
13 | 2020 | A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing | Wu, Y.-C.; Chen, Y.-L.; Yang, C.-H.; Lee, C.-H.; Yu, C.-Y.; Chang, N.-S.; Chen, L.-C.; Chang, J.-R.; Lin, C.-P.; Chen, H.-L.; Chen, C.-S.; Hung, J.-H.; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
14 | 2023 | A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing | Chen, Yen Lung; Yang, Chung Hsuan; Wu, Yi Chung; Lee, Chao Hsi; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; Hung, Jui Hung; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
15 | 2016 | Error-resilient sequential cells with successive time borrowing for stochastic computing | Liu, W.-C.; Chan, C.-D.; Huang, S.-A.; Lo, C.-W.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
16 | 2008 | DSP architecture optimization in Matlab/Simulink environment | CHIA-HSIANG YANG ; N; a, R.; Yang, C.-H.; Markovic, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
17 | 2021 | Design optimization for ADMM-Based SVM Training Processor for Edge Computing | Huang S.-A; Hsieh Y.-Y; CHIA-HSIANG YANG | 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021 | |||
18 | 2004 | Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems | Yang, Chia-Hsiang ; Lin, Yu-Hsuan; Lin, Shih-Chun; Chiueh, Tzi-Dar | 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04 | 7 | 0 | |
19 | 2016 | Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease | T.-I. Chou; S.-W. Chiu; K.-H. Chang; Y.-J. Chen; C.-T. Tang; C.-H. Shih; C.-C. Hsieh; M.-F. Chang; C.-H. Yang; H. Chiueh; K.-T. Tang; CHIA-HSIANG YANG | IEEE Biomedical Circuits & Systems Conf. (BioCAS) | 0 | 0 | |
20 | 2015 | A Concept of Heterogeneous Circuits with Epitaxial Tunnel Layer Tunnel FETs | J.-H. Hung; P.-Y. Wang; B.-Y. Tsui; C.-H. Yang; CHIA-HSIANG YANG | Int. Conf. Solid State Devices and Materials (SSDM) | 0 | 0 | |
21 | 2021 | A color doppler processing engine with an adaptive clutter filter for portable ultrasound imaging devices | Lo Y.-L; CHIA-HSIANG YANG | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | |||
22 | 2017 | A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing | X.-H. Qian; Y.-C. Wu; T.-Y. Yang; C.-H. Cheng; H.-C. Chu; W.-H. Cheng; T.-Y. Yen,T.-H. Lin; Y.-J. Lin; Y.-C. Lee; J.-H. Chang; S.-T. Lin; S.-H. Li; T.-C. Wu; C.-C. Huang; C.-F. Lee; C.-H. Yang; C.-C. Hung; T.-S. Chi; C.-H. Liu; M.-D. Ker; C.-Y. Wu; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI) | 11 | 0 | |
23 | 2017 | An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors | W.-C. Sun; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | IEEE Vehicular Technology Conference | 1 | 0 | |
24 | 2011 | An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensing | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Marković, D.; Čabrić, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
25 | 2008 | A multi-core sphere decoder VLSI architecture for MIMO communications | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
26 | 2011 | A hardware-efficient VLSI architecture for hybrid sphere-MCMC detection | CHIA-HSIANG YANG ; Yuan, F.-L.; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
27 | 2013 | A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control | CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
28 | 2008 | A flexible VLSI architecture for extracting diversity and spatial multiplexing gains in MIMO channels | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE International Conference on Communications | |||
29 | 2016 | A 98.6μW acoustic signal processor for fully-implantable cochlear implants | Liu, H.-M.; Lin, Y.-J.; Lee, Y.-C.; Lee, C.-Y.; CHIA-HSIANG YANG | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 | |||
30 | 2015 | A 794Mbps 135mW iterative detection and decoding receiver for 4x4 LDPC-coded MIMO systems in 40nm | CHIA-HSIANG YANG ; Wu, W.-H.; Sun, W.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
31 | 2011 | A 75μW, 16-channel neural spike-sorting processor with unsupervised clustering | Karkare, Vaibhav; Gibson, Sarah; CHIA-HSIANG YANG ; Chen, Henry; Marković, Dejan | IEEE Symposium on VLSI Circuits | |||
32 | 2011 | A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
33 | 2010 | A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs | CHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
34 | 2013 | A 28.6μW mixed-signal processor for epileptic seizure detection | CHIA-HSIANG YANG ; Chen, T.-J.; Lee, S.-C.; Yang, C.-H.; Chiu, C.-F.; Chiueh, H.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
35 | 2009 | A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOS | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | ESSCIRC 2009 - 35th European Solid-State Circuits Conference | |||
36 | 2013 | A 191μW BPSK demodulator for data and power telemetry in biomedical implants | CHIA-HSIANG YANG ; Wang, L.-L.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | ACM Great Lakes Symposium on VLSI, GLSVLSI | |||
37 | 2005 | A 1.2V 6.7mW impulse-radio UWB baseband transceiver | CHIA-HSIANG YANG ; Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
38 | 2022 | A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction | Hsieh Y.-Y; Lin Y.-C; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 7 | 0 | |
39 | 2022 | A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping | Yang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings | 0 | 0 | |
40 | 2023 | A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition | Tong, Tzu Wei; Hsieh, Yi Yen; Chen, Tai Jung; CHIA-HSIANG YANG | 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023 | |||
41 | 2017 | A 501mW 7.6lGb/s integrated message-passing detector and decoder for polar-coded massive MIMO systems | Chen Y.-T; Cheng C.-C; Tsai T.-L; Sun W.-C; Ueng Y.-L; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
42 | 2017 | A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems | Y.-T. Chen; C.-C. Cheng; T.-L. Tsai; W.-C. Sun; Y.-L. Ueng; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI) | 19 | 0 | |
43 | 2022 | A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing | Lo, Yu Chen; Wu, Yi Chung; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
44 | 2022 | A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training | Fu, Zih Sing; Lee, Yu Chi; Park, Alex; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 3 | 0 | |
45 | 2023 | A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing | Lin, Liang Hsin; Fu, Zih Sing; Chen, Po Shao; Yang, Bo Yin; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
46 | 2021 | 4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images | Shen H.-Y; Lee Y.-C; Tong T.-W; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
47 | 2024 | 30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization | Chu, Yi Chen; Lin, Yu Cheng; Lo, Yu Chen; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
48 | 2018 | A 2กั2-16กั16 Reconfigurable GGMD Processor for MIMO Communication Systems | Chiang, C.-H.; Huang, S.-A.; Chen, C.-E.; CHIA-HSIANG YANG | Proceedings - IEEE International Symposium on Circuits and Systems | |||
49 | 2018 | A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems | C.-H. Chiang; S.-A. Huang; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | |||
50 | 2023 | A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow | Du, Cheng Yan; Tsai, Chieh Fu; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
51 | 2021 | A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring | Chen P.-S; Chen Y.-L; Lee Y.-C; Fu Z.-S; CHIA-HSIANG YANG | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference | |||
52 | 2022 | A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality | Huang, Wen Cong; Lin, I. Ting; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 1 | 0 | |
53 | 2023 | A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing | Lin, Yu Cheng; Park, Chanmin; Zhao, Wenda; Sun, Nan; Chae, Youngcheol; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
54 | 2014 | 24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia | CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
55 | 2024 | 2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems | Lee, Tang; Chen, Ting Yang; I-HSUAN LIU; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
56 | 2019 | A 2.25 TOPS/W fully-integrated deep CNN learning processor with on-chip training | Lu C.-H; Wu Y.-C; CHIA-HSIANG YANG | Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 | 14 | 0 | |
57 | 2019 | A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices | Lee, Y.-C.; Chi, T.-S.; CHIA-HSIANG YANG | Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 | |||
58 | 2023 | A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices | Lo, Yi Lin; Lo, Yu Chen; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
59 | 2017 | A 135mW Fully Integrated Data Processor for Next-Generation Sequencing | Y.-C. Wu; J.-H. Hung; C.-H. Yang; CHIA-HSIANG YANG | Int. Solid-State Circuits Conference (ISSCC) | 8 | 0 | |
60 | 2018 | A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals | Y.-Z. Wang; Y.-P. Wang; Y.-C. Wu; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI Circuits) | 3 | 0 | |
61 | 2018 | A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals | Wang Y.-Z; Wang Y.-P; Wu Y.-C; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
62 | 2020 | A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems | Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
63 | 2018 | A 1.9-mW SVM Processor with On-chip Active Learning for Epileptic Seizure Control | Huang S.-A.; Chang K.-C.; HORNG-HUEI LIOU ; Yang C.-H.; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI Circuits) | 9 | 0 | |
64 | 2020 | A 1.5£gJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots | Chung, C.; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
65 | 2022 | A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI | Tsai, Yu Hsuan; YI-CHENG LIN; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Shi Hao; Chen, Chi Shi; CHIA-HSIANG YANG | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings | 0 | 0 | |
66 | 2021 | A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices | Yu S.-J; Lee Y.-C; CHIA-HSIANG YANG | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference |