第 1 到 123 筆結果,共 123 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2024 | 30.4 A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization | Chu, Yi Chen; Lin, Yu Cheng; Lo, Yu Chen; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
2 | 2024 | 2.6 A 131mW 6.4Gbps 256×32 Multi-User MIMO OTFS Detector for Next-Gen Communication Systems | Lee, Tang; Chen, Ting Yang; I-HSUAN LIU; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
3 | 2023 | Clinical utility of anal sphincter relaxation integral in water-perfused and solid-state high-resolution anorectal manometry | JIA-FENG WU ; Lin, Yu-Cheng; CHIA-HSIANG YANG ; PING-HUEI TSENG ; I-JUNG TSAI ; WEN-HSI LIN ; WEN-MING HSU | Journal of the Formosan Medical Association = Taiwan yi zhi | 1 | 0 | |
4 | 2023 | An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices | Yu, Sheng Jung; Lee, Yu Chi; Lin, Liang Hsin; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
5 | 2023 | A 40-nm 91-mW, 90-fps Learning-Based Full HD Super-Resolution Accelerator | Shen, Hsueh Yen; Lee, Yu Chi; Tong, Tzu Wei; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
6 | 2023 | A 169mW Fully-Integrated Ultrasound Imaging Processor Supporting Advanced Modes for Hand-Held Devices | Lo, Yi Lin; Lo, Yu Chen; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
7 | 2023 | A 73.8K Inference/mJ SVM Learning Accelerator for Brain Pattern Recognition | Tong, Tzu Wei; Hsieh, Yi Yen; Chen, Tai Jung; CHIA-HSIANG YANG | 2023 IEEE Asian Solid-State Circuits Conference, A-SSCC 2023 | |||
8 | 2023 | A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing | Chen, Yen Lung; Yang, Chung Hsuan; Wu, Yi Chung; Lee, Chao Hsi; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; Hung, Jui Hung; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
9 | 2023 | A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow | Du, Cheng Yan; Tsai, Chieh Fu; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 0 | 0 | |
10 | 2023 | A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring | Chen, Po Shao; Chen, Yen Lung; Lee, Yu Chi; Fu, Zih Sing; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
11 | 2023 | A 96.2-nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction | Hsieh, Yi Yen; Lin, Yu Cheng; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 1 | 1 | |
12 | 2023 | An FM-index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-end Short-read Mapping | Yang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | 0 | 0 | |
13 | 2023 | A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing | Lin, Yu Cheng; Park, Chanmin; Zhao, Wenda; Sun, Nan; Chae, Youngcheol; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
14 | 2023 | A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing | Lin, Liang Hsin; Fu, Zih Sing; Chen, Po Shao; Yang, Bo Yin; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
15 | 2022 | Achieving Accurate Automatic Sleep Apnea/Hypopnea Syndrome Assessment Using Nasal Pressure Signal | Ying-Sheng Lin; Yi-Pao Wu; Yi-Chung Wu; PEI-LIN LEE ; CHIA-HSIANG YANG | IEEE Journal of Biomedical and Health Informatics | 2 | 2 | |
16 | 2022 | A 28-nm 25.1 TOPS/W Sparsity-Aware CNN-GCN Deep Learning SoC for Mobile Augmented Reality | Huang, Wen Cong; Lin, I. Ting; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Chi Shi; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 1 | 0 | |
17 | 2022 | A 1.3mW Speech-to-Text Accelerator with Bidirectional Light Gated Recurrent Units for Edge AI | Tsai, Yu Hsuan; YI-CHENG LIN; Chen, Wen Ching; Lin, Liang Yi; Chang, Nian Shyang; CHUN-PIN LIN; Chen, Shi Hao; Chen, Chi Shi; CHIA-HSIANG YANG | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings | 0 | 0 | |
18 | 2022 | Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression | Kao, Chen Chien; Hsieh, Yi Yen; Chen, Chao Hung; CHIA-HSIANG YANG | Midwest Symposium on Circuits and Systems | 1 | 0 | |
19 | 2022 | A 75.6M Base-pairs/s FPGA Accelerator for FM-index Based Paired-end Short-Read Mapping | Yang, Chung Hsuan; Wu, Yi Chung; Chen, Yen Lung; Lee, Chao Hsi; Hung, Jui Hung; CHIA-HSIANG YANG | 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022 - Proceedings | 0 | 0 | |
20 | 2022 | A 40-nm 646.6TOPS/W Sparsity-Scaling DNN Processor for On-Device Training | Fu, Zih Sing; Lee, Yu Chi; Park, Alex; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 3 | 0 | |
21 | 2022 | A 44.3mW 62.4fps Hyperspectral Image Processor for MAV Remote Sensing | Lo, Yu Chen; Wu, Yi Chung; CHIA-HSIANG YANG | Digest of Technical Papers - Symposium on VLSI Technology | 0 | 0 | |
22 | 2022 | CAS Research and Teaching Activities in Taiwan [CAS in the World] | Chang, Robert Chen Hao; Hwang, Yin Tsung; Lin, Yuan Pei; CHIA-HSIANG YANG | IEEE Circuits and Systems Magazine | 0 | 0 | |
23 | 2022 | A 96.2nJ/class Neural Signal Processor with Adaptable Intelligence for Seizure Prediction | Hsieh Y.-Y; Lin Y.-C; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 7 | 0 | |
24 | 2021 | Bolus transit of upper esophageal sphincter on high-resolution impedance manometry study correlate with the laryngopharyngeal reflux symptoms | JIA-FENG WU ; WEI-CHUNG HSU ; I-JUNG TSAI ; Tong, TW; Lin, YC; CHIA-HSIANG YANG ; PING-HUEI TSENG | SCIENTIFIC REPORTS | 2 | 2 | |
25 | 2021 | A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing | CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
26 | 2021 | Design of a Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its in Vivo Verification | Liu C.-H; Wu, Chung-Yu; Ker, Ming-Dou; Liu, Chien-Hao ; Hung, Chung-Chih; Yang, Chia-Hsiang ; Lee, Chia-Fone; Chang, Po-Chih; Tu, Yen-Fu; Tang, Li-Yang; Chen, Ching-Yuan; CHIEN-HAO LIU | IEEE Journal of Solid-State Circuits | 12 | 8 | |
27 | 2021 | A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome | Chen Y.-L; Chang B.-Y; CHIA-HSIANG YANG ; TZI-DAR CHIUEH | IEEE Transactions on Parallel and Distributed Systems | 8 | 15 | |
28 | 2021 | 4.7 A 91mW 90fps Super-Resolution Processor for Full HD Images | Shen H.-Y; Lee Y.-C; Tong T.-W; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
29 | 2021 | A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring | Chen P.-S; Chen Y.-L; Lee Y.-C; Fu Z.-S; CHIA-HSIANG YANG | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference | |||
30 | 2021 | A 1.18mW Double Ratchet Cryptographic Processor with Backward Secrecy for IoT Devices | Yu S.-J; Lee Y.-C; CHIA-HSIANG YANG | Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference | |||
31 | 2021 | A 1.5-μJ/Task Path-Planning Processor for 2-D/3-D Autonomous Navigation of Microrobots | Chung C; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
32 | 2021 | Hybrid Precoding Baseband Processor for 64x 64 Millimeter Wave MIMO Systems | Kao C; Chen C; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
33 | 2021 | Design optimization for ADMM-Based SVM Training Processor for Edge Computing | Huang S.-A; Hsieh Y.-Y; CHIA-HSIANG YANG | 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits and Systems, AICAS 2021 | |||
34 | 2021 | A color doppler processing engine with an adaptive clutter filter for portable ultrasound imaging devices | Lo Y.-L; CHIA-HSIANG YANG | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings | |||
35 | 2020 | Pressure-impedance analysis: Assist the diagnosis and classification of ineffective esophageal motility disorder | JIA-FENG WU ; I-JUNG TSAI ; Tong, TW; YI-CHENG LIN ; CHIA-HSIANG YANG ; PING-HUEI TSENG | JOURNAL OF GASTROENTEROLOGY AND HEPATOLOGY | 4 | 3 | |
36 | 2020 | A 1.9-mW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control | Huang, S.-A.; Chang, K.-C.; HORNG-HUEI LIOU ; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 32 | 23 | |
37 | 2020 | Improved design and in vivo animal tests of bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulation and neural action potential acquisition | Wang S.-H; Huang Y.-K; Chen C.-Y; Lee C.-F; Yang C.-H; Hung C.-C; Liu C.-H; Ker M.-D; CHIEN-HAO LIU ; CHIA-HSIANG YANG | 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 | 3 | 0 | |
38 | 2020 | A 1.5 mW Programmable Acoustic Signal Processor for Hearing Assistive Devices with Speech Intelligibility Enhancement | Lin Y.-J; Lee Y.-C; Liu H.-M; Chiueh H; Chi T.-S; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
39 | 2020 | Digital Logic and Asynchronous Datapath with Heterogeneous TFET-MOSFET Structure for Ultralow-Energy Electronics | Hung, J.; Wang, P.; Lo, Y.; Yang, C.; Tsui, B.; CHIA-HSIANG YANG | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits | |||
40 | 2020 | A 1.5£gJ/Task Path-Planning Processor for 2D/3D Autonomous Navigation of Micro Robots | Chung, C.; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
41 | 2020 | A 1.96 Gb/s Massive MU-MIMO Detector for Next-Generation Cellular Systems | Wen, C.-C.; Lee, Y.-C.; Wu, Y.-C.; Kao, C.-C.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
42 | 2020 | A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing | Wu, Y.-C.; Chen, Y.-L.; Yang, C.-H.; Lee, C.-H.; Yu, C.-Y.; Chang, N.-S.; Chen, L.-C.; Chang, J.-R.; Lin, C.-P.; Chen, H.-L.; Chen, C.-S.; Hung, J.-H.; CHIA-HSIANG YANG | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | |||
43 | 2020 | Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS | Chiueh, H.; Yang, C.-H.; Wen, C.H.-P.; Yang, C.-G.; Chien, P.-H.; Hung, C.-Y.; Chen, Y.-J.; Wang, Y.-P.; Chiu, C.-F.; Lin, J.; CHIA-HSIANG YANG | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | |||
44 | 2020 | Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax | Wang Y.-P; Wen C.-C; Kao C.-C; Huang C.-J; Liu D.-Z; CHIA-HSIANG YANG | 2020 IEEE Global Communications Conference, GLOBECOM 2020 - Proceedings | |||
45 | 2020 | A 2.17-mw acoustic dsp processor with cnn-fft accelerators for intelligent hearing assistive devices | Lee, Y.-C.; Chi, T.-S.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
46 | 2019 | A 2.25 TOPS/W fully-integrated deep CNN learning processor with on-chip training | Lu C.-H; Wu Y.-C; CHIA-HSIANG YANG | Proceedings - 2019 IEEE Asian Solid-State Circuits Conference, A-SSCC 2019 | 14 | 0 | |
47 | 2019 | A 2.17mW Acoustic DSP Processor with CNN-FFT Accelerators for Intelligent Hearing Aided Devices | Lee, Y.-C.; Chi, T.-S.; CHIA-HSIANG YANG | Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 | |||
48 | 2019 | A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals | Wang, Y.-Z.; Wang, Y.-P.; Wu, Y.-C.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
49 | 2019 | A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. | Huang, Shuo-An; CHIA-HSIANG YANG | CoRR | |||
50 | 2019 | Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. | Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; CHIA-HSIANG YANG | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019 | |||
51 | 2019 | An integrated message-passing detector and decoder for polar-coded massive MU-MIMO systems | Chen, Y.-T.; Sun, W.-C.; Cheng, C.-C.; Tsai, T.-L.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
52 | 2019 | An LDPC-Coded SCMA receiver with multi-user iterative detection and decoding | Sun, W.-C.; Su, Y.-C.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
53 | 2019 | Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems | Sun, W.-C.; Chen, Y.-T.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Signal Processing | |||
54 | 2018 | A 12.6mW 573-2,901KS/s Reconfigurable Processor for Reconstruction of Compressively-Sensed Physiological Signals | Y.-Z. Wang; Y.-P. Wang; Y.-C. Wu; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI Circuits) | 3 | 0 | |
55 | 2018 | Performance of pre-production band 1 receiver for the Atacama Large Millimeter/submillimeter Array (ALMA) | Huang Y.-D.T; Morata O; Koch P.M; Kemper C; Hwang Y.-J; Chiong C.-C; Ho P.T.P; Chu Y.-H; Huang C.-D; Liu C.-T; Hsieh F.-C; Tseng Y.-H; CHIA-HSIANG YANG ; Tsay J.J; Chang T; Ho C.-T; Chiang P.-H; Chang C.-C; Jian S.-T; Hsu S.-P; Chien C; Iguchi S; Asayama S; Iono D; Gonzalez A; Effland J; Saini K; Pospieszalski M; Henke D; Yeung K; Finger R; Tapia V; Reyes N. | Proceedings of SPIE - The International Society for Optical Engineering | 5 | 0 | |
56 | 2018 | A 1.9-mW SVM Processor with On-chip Active Learning for Epileptic Seizure Control | Huang S.-A.; Chang K.-C.; HORNG-HUEI LIOU ; Yang C.-H.; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI Circuits) | 9 | 0 | |
57 | 2018 | Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC) | Lin, T.-H.; Yang, C.-H.; TSUNG-HSIEN LIN ; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
58 | 2018 | Distal contractile to impedance integral ratio assist the diagnosis of pediatric ineffective esophageal motility disorder | JIA-FENG WU ; Chung, Chieh; PING-HUEI TSENG ; I-JUNG TSAI ; Lin, Yi-Cheng; CHIA-HSIANG YANG ; YI-CHENG LIN | Pediatric Research | 4 | 4 | |
59 | 2018 | A 2x2-16x16 Reconfigurable GGMD Processor for MIMO Communication Systems | C.-H. Chiang; S.-A. Huang; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | |||
60 | 2018 | Diagnostic Role of Anal Sphincter Relaxation Integral in High-Resolution Anorectal Manometry for Hirschsprung Disease in Infants | JIA-FENG WU ; CHENG-HSUN LU ; CHIA-HSIANG YANG ; I-JUNG TSAI | Journal of Pediatrics | 23 | 10 | |
61 | 2018 | Massive MIMO detection VLSI design. | CHIA-HSIANG YANG | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 | |||
62 | 2018 | A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip | T.-I Chou; K.-H. Chang; J.-Y. Jhang; S.-W. Chiu; G. Wang; CHIA-HSIANG YANG ; H. Chiueh; H. Chen; C.-C. Hsieh; M.-F. Chang; K.-T. Tang | IEEE Transactions on Circuits and Systems II | 5 | 4 | |
63 | 2018 | A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems | C.-Y. Yeh; T.-C. Chu; C.-E. Chen; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Paper | 3 | 3 | |
64 | 2018 | A 12.6MW 573-2,901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals | Wang Y.-Z; Wang Y.-P; Wu Y.-C; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
65 | 2018 | A 2กั2-16กั16 Reconfigurable GGMD Processor for MIMO Communication Systems | Chiang, C.-H.; Huang, S.-A.; Chen, C.-E.; CHIA-HSIANG YANG | Proceedings - IEEE International Symposium on Circuits and Systems | |||
66 | 2017 | A 501mW 7.61Gb/s Integrated Message-Passing Detector and Decoder for Polar-Coded Massive MIMO Systems | Y.-T. Chen; C.-C. Cheng; T.-L. Tsai; W.-C. Sun; Y.-L. Ueng; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI) | 19 | 0 | |
67 | 2017 | A 135-mW Fully Integrated Data Processor for Next-Generation Sequencing | Wu, Y.-C.; Chang, C.-H.; Hung, J.-H.; CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | |||
68 | 2017 | A Flexible Geometric Mean Decomposition Processor for MIMO Communication Systems | Y.-C. Tsai; C.-E. Chen; C.-H. Yang; CHIA-HSIANG YANG | IEEE Transaction on Circuits & Systems I (TCAS-I) | 5 | 5 | |
69 | 2017 | A 5.28-Gbps LDPC Decoder with Time-domain Signal Processing for IEEE 802.15.3c Applications | M.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
70 | 2017 | Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables | H.-T. Lin; Y.-C. Wu; P.-H. Hsieh; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | 1 | 0 | |
71 | 2017 | A 135mW Fully Integrated Data Processor for Next-Generation Sequencing | Y.-C. Wu; J.-H. Hung; C.-H. Yang; CHIA-HSIANG YANG | Int. Solid-State Circuits Conference (ISSCC) | 8 | 0 | |
72 | 2017 | An Area-Efficient Multi-Mode LLR Computing Engine for MMSE-Based MIMO Detectors | W.-C. Sun; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | IEEE Vehicular Technology Conference | 1 | 0 | |
73 | 2017 | Extreme index finder and finding method thereof | M.-R. Li; C.-H. Yang; Y.-L. Ueng; CHIA-HSIANG YANG | ||||
74 | 2017 | A Bone-Guided Cochlear Implant CMOS Microsystem Preserving Acoustic Hearing | X.-H. Qian; Y.-C. Wu; T.-Y. Yang; C.-H. Cheng; H.-C. Chu; W.-H. Cheng; T.-Y. Yen,T.-H. Lin; Y.-J. Lin; Y.-C. Lee; J.-H. Chang; S.-T. Lin; S.-H. Li; T.-C. Wu; C.-C. Huang; C.-F. Lee; C.-H. Yang; C.-C. Hung; T.-S. Chi; C.-H. Liu; M.-D. Ker; C.-Y. Wu; CHIA-HSIANG YANG | Int. Symposium on VLSI Circuits (VLSI) | 11 | 0 | |
75 | 2017 | A 501mW 7.6lGb/s integrated message-passing detector and decoder for polar-coded massive MIMO systems | Chen Y.-T; Cheng C.-C; Tsai T.-L; Sun W.-C; Ueng Y.-L; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits, Digest of Technical Papers | |||
76 | 2017 | A 5.28-Gb/s LDPC Decoder With Time-Domain Signal Processing for IEEE 802.15.3c Applications | Li, M.-R.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
77 | 2016 | Design of a 0.5V 1.68mW Nose-on-a-Chip for Rapid Screen of Chronic Obstructive Pulmonary Disease | T.-I. Chou; S.-W. Chiu; K.-H. Chang; Y.-J. Chen; C.-T. Tang; C.-H. Shih; C.-C. Hsieh; M.-F. Chang; C.-H. Yang; H. Chiueh; K.-T. Tang; CHIA-HSIANG YANG | IEEE Biomedical Circuits & Systems Conf. (BioCAS) | 0 | 0 | |
78 | 2016 | Method and system for constrained power allocation in the multi-input multi-output systems | C.-H. Yang; C.-E. Chen; C.-W. Jou; CHIA-HSIANG YANG | ||||
79 | 2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | ||||
80 | 2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | ||||
81 | 2016 | Data allocating apparatus, signal processing apparatus, and data allocating method | C.-H. Yang; H.-M. Liu; Y.-J. Lin; CHIA-HSIANG YANG | ||||
82 | 2016 | sBWT: Memory Efficient Implementation of the Hardware-acceleration-friendly Schindler Transform for the Fast Biological Sequence Mapping | C.-H. Chang; M.-T. Chou; Y.-C. Wu; T.-W. Hong; Y.-L. Li; C.-H. Yang; J.-H. Hung; CHIA-HSIANG YANG | Bioinformatics | 8 | 7 | |
83 | 2016 | Sampling Circuit and Master-Slave Flip-Flop | S.-J. Jou; C.-H. Yang; W.-C. Liu; C.-W. Lo; C.-D. Chan; CHIA-HSIANG YANG | ||||
84 | 2016 | Energy Recycling Systems and Recycling Method Thereof | C.-H. Yang; P.-H. Hsieh; C.-Y. Lee; CHIA-HSIANG YANG | ||||
85 | 2016 | A 98.6μW acoustic signal processor for fully-implantable cochlear implants | Liu, H.-M.; Lin, Y.-J.; Lee, Y.-C.; Lee, C.-Y.; CHIA-HSIANG YANG | 2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 | |||
86 | 2016 | Error-resilient sequential cells with successive time borrowing for stochastic computing | Liu, W.-C.; Chan, C.-D.; Huang, S.-A.; Lo, C.-W.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | |||
87 | 2016 | A Standard-Cell-Design-Flow Compatible Energy-Recycling Logic With 70% Energy Saving | Lee, C.-Y.; Hsieh, P.-H.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
88 | 2015 | A Concept of Heterogeneous Circuits with Epitaxial Tunnel Layer Tunnel FETs | J.-H. Hung; P.-Y. Wang; B.-Y. Tsui; C.-H. Yang; CHIA-HSIANG YANG | Int. Conf. Solid State Devices and Materials (SSDM) | 0 | 0 | |
89 | 2015 | An iterative geometric mean decomposition algorithm for MIMO communications systems | CHIA-HSIANG YANG ; Chen, C.-E.; Tsai, Y.-C.; CHIA-HSIANG YANG | IEEE Transactions on Wireless Communications | |||
90 | 2015 | A 794Mbps 135mW iterative detection and decoding receiver for 4x4 LDPC-coded MIMO systems in 40nm | CHIA-HSIANG YANG ; Wu, W.-H.; Sun, W.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
91 | 2015 | A Systolic Array Based GTD Processor With a Parallel Algorithm | CHIA-HSIANG YANG ; Yang, C.-H.; Chou, C.-W.; Hsu, C.-S.; Chen, C.-E.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
92 | 2015 | A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia | CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | |||
93 | 2015 | An iterative detection and decoding receiver for LDPC-coded MIMO systems | CHIA-HSIANG YANG ; Sun, W.-C.; Wu, W.-H.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
94 | 2014 | A fully integrated 8-channel closed-loop neural-prosthetic cmos soc for real-time epileptic seizure control | CHIA-HSIANG YANG et al. | IEEE Journal of Solid-State Circuits | 183 | 162 | |
95 | 2014 | A 5.4 μw soft-decision bch decoder for wireless body area networks | CHIA-HSIANG YANG ; Yang, C.-H.; Huang, T.-Y.; Li, M.-R.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
96 | 2014 | A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applications | CHIA-HSIANG YANG ; Cheng, C.-C.; Yang, J.-D.; Lee, H.-C.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
97 | 2014 | An 81.6 μW FastICA Processor for Epileptic Seizure Detection | CHIA-HSIANG YANG ; Yang, C.-H.; Shih, Y.-H.; Chiueh, H.; CHIA-HSIANG YANG | IEEE Transactions on Biomedical Circuits and Systems | |||
98 | 2014 | 24.5 A 0.5V 1.27mW nose-on-a-chip for rapid diagnosis of ventilator-associated pneumonia | CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
99 | 2014 | Unequal Bit-reliability Information Storage Method for Communication and Storage Systems | Y.-L. Ueng; C.-H. Yang; M. R. Li; CHIA-HSIANG YANG | ||||
100 | 2013 | A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control | CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
101 | 2013 | A hierarchical approach for online temporal lobe seizure detection in long-term intracranial EEG recordings | CHIA-HSIANG YANG ; Liang, S.-F.; Chen, Y.-C.; Wang, Y.-L.; Chen, P.-T.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | Journal of Neural Engineering | |||
102 | 2013 | Power and area reduction in multi-stage addition using operand segmentation | CHIA-HSIANG YANG ; Chan, C.-D.; Liu, W.-C.; Yang, C.-H.; Jou, S.-J.; CHIA-HSIANG YANG | 2013 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT 2013 | |||
103 | 2013 | A 191μW BPSK demodulator for data and power telemetry in biomedical implants | CHIA-HSIANG YANG ; Wang, L.-L.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | ACM Great Lakes Symposium on VLSI, GLSVLSI | |||
104 | 2013 | A 28.6μW mixed-signal processor for epileptic seizure detection | CHIA-HSIANG YANG ; Chen, T.-J.; Lee, S.-C.; Yang, C.-H.; Chiu, C.-F.; Chiueh, H.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
105 | 2012 | A 7.4-mW 200-MS/s wideband spectrum sensing digital baseband processor for cognitive radios | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
106 | 2012 | Power and area minimization of reconfigurable FFT processors: A 3GPP-LTE example | CHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Markovi?, D.; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | |||
107 | 2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection | CHIA-HSIANG YANG ; Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | 2012 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 | |||
108 | 2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. | Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming; CHIA-HSIANG YANG | Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012 | |||
109 | 2011 | A 7.4mW 200MS/s wideband spectrum sensing digital baseband processor for cognitive radios | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Čabrić, D.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
110 | 2011 | A hardware-efficient VLSI architecture for hybrid sphere-MCMC detection | CHIA-HSIANG YANG ; Yuan, F.-L.; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
111 | 2011 | An energy-efficient VLSI architecture for cognitive radio wideband spectrum sensing | CHIA-HSIANG YANG ; Yu, T.-H.; Yang, C.-H.; Marković, D.; Čabrić, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
112 | 2011 | A 75μW, 16-channel neural spike-sorting processor with unsupervised clustering | Karkare, Vaibhav; Gibson, Sarah; CHIA-HSIANG YANG ; Chen, Henry; Marković, Dejan | IEEE Symposium on VLSI Circuits | |||
113 | 2010 | AMiBA wideband analog correlator | Li, C.-T.; TZI-DAR CHIUEH ; JIUN-HUEI PROTY WU ; CHIA-HSIANG YANG et al. | Astrophysical Journal | 16 | 17 | |
114 | 2010 | A 5.8mW 3GPP-LTE compliant 8×8 MIMO sphere decoder chip with soft-outputs | CHIA-HSIANG YANG ; Yang, C.-H.; Yu, T.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
115 | 2009 | A flexible DSP architecture for MIMO sphere decoding | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | |||
116 | 2009 | A 2.89mW 50GOPS 16 × 16 16-core MIMO sphere decoder in 90nm CMOS | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | ESSCIRC 2009 - 35th European Solid-State Circuits Conference | |||
117 | 2009 | The yuan-tseh lee array for microwave background anisotropy | Ho, P.T.P.; Altamirano, P.; Chang, C.-H.; Chang, S.-H.; Chang, S.-W.; Chen, C.-C.; Chen, K.-J.; Chen, M.-T.; Han, C.-C.; Ho, W.M.; Huang, Y.-D.; Hwang, Y.-J.; Ib?ez-Romano, F.; Jiang, H.; Koch, P.M.; Kubo, D.Y.; Li, C.-T.; Lim, J.; Lin, K.-Y.; Liu, G.-C.; Lo, K.-Y.; Ma, C.-J.; Martin, R.N.; Martin-Cocher, P.; Molnar, S.M.; Ng, K.-W.; Nishioka, H.; O'Connell, K.E.; Oshiro, P.; Patt, F.; Raffin, P.; Umetsu, K.; Wei, T.; Wu, J.-H.P.; Chiueh, T.-D.; Chiueh, T.; Chu, T.-H.; Huang, C.-W.L.; Hwang, W.Y.P.; Liao, Y.-W.; Lien, C.-H.; Wang, F.-C.; Wang, H.; Wei, R.-M.; Yang, C.-H.; Kesteven, M.; Kingsley, J.; Sinclair, M.M.; Wilson, W.; Birkinshaw, M.; Liang, H.; Lancaster, K.; Park, C.-G.; Pen, U.-L.; TZI-HONG CHIUEH ; W-Y HWANG ; CHIA-HSIANG YANG ; Chang, Chia-Hao; TAH HSIUNG CHU ; FU-CHENG WANG ; HUEI WANG ; TZI-DAR CHIUEH ; JIUN-HUEI PROTY WU | Astrophysical Journal | 38 | 40 | |
118 | 2008 | A multi-core sphere decoder VLSI architecture for MIMO communications | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | GLOBECOM - IEEE Global Telecommunications Conference | |||
119 | 2008 | A flexible VLSI architecture for extracting diversity and spatial multiplexing gains in MIMO channels | CHIA-HSIANG YANG ; Yang, C.-H.; Marković, D.; CHIA-HSIANG YANG | IEEE International Conference on Communications | |||
120 | 2008 | DSP architecture optimization in Matlab/Simulink environment | CHIA-HSIANG YANG ; N; a, R.; Yang, C.-H.; Markovic, D.; CHIA-HSIANG YANG | IEEE Symposium on VLSI Circuits | |||
121 | 2005 | A 1.2V 6.7mW impulse-radio UWB baseband transceiver | CHIA-HSIANG YANG ; Yang, C.-H.; Chen, K.-H.; Chiueh, T.-D.; CHIA-HSIANG YANG | IEEE International Solid-State Circuits Conference | |||
122 | 2004 | Design of a low-complexity receiver for impulse-radio ultra-wideband communication systems | Yang, Chia-Hsiang ; Lin, Yu-Hsuan; Lin, Shih-Chun; Chiueh, Tzi-Dar | 2004 International Symposium on Circuits and Systems, 2004. ISCAS '04 | 7 | 0 | |
123 | 2004 | A wideband analog correlator system for AMiBA | Li, C.-T.; Kubo, D.; Han, C.-C.; Chen, C.-C.; Chen, M.-T.; Lien, C.-H.; Wang, H.; Wei, R.-M.; Yang, C.-H.; Chiueh, T.-D.; Peterson, J.; Kesteven, M.; TZI-DAR CHIUEH ; CHIA-HSIANG YANG ; HUEI WANG | Proceedings of SPIE - The International Society for Optical Engineering | 18 | 0 |