第 1 到 57 筆結果,共 57 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2008 | 超大型奈米積體電路無格線式全晶片繞線系統之研究(3/3) | 張耀文 | ||||
2 | 2008 | 兆級晶片系統前瞻技術研究-子計畫六:兆級晶片系統實體整合之研究(2/3) | 張耀文 | ||||
3 | 2008 | BioRoute: A network-flow-based routing algorithm for the synthesis of digital microfluidic biochips | Yuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 77 | 55 | |
4 | 2008 | Full-Chip Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, B. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 46 | ||
5 | 2008 | NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints | Chen, T.-C.; Jiang, Z.-W.; Hsu, T.-C.; Chen, H.-C.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 236 | 200 | |
6 | 2008 | A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning | Chen, Tung-Chieh; Chang, Yao-Wen ; Lin, Shyh-Chang | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 24 | ||
7 | 2008 | Effective Wire Models for X-Architecture Placement | Chen, Tung-Chieh; Chuang, Yi-Lin; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | ||
8 | 2007 | Temporal floorplanning using the three-dimensional transitive closure subGraph | Yuh, Ping-Hung; YAO-WEN CHANG ; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | 21 | 17 | |
9 | 2007 | Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence | Liu, Chen-Wei; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
10 | 2007 | Multilevel Full-Chip Routing With Testability and Yield Enhancement | Li, Katherine Shu-Min; Chang, Yao-Wen ; Lee, Chung-Len; Su, Chauchin; Chen, Jwu E. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | ||
11 | 2007 | An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles | Su, B.-Y.; Hu, J.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 2 | |
12 | 2007 | 3D Video Applications and Intelligent Video Surveillance Camera and its VLSI Design | Chien, hao-Yi; Shih, Chi-Sheng ; Ku, Mong-Kai; Yang, Chia-Lin ; Chang, Yao-Wen ; Kuo, Tei-Wei ; Chen, Liang-Gee | 2007 IEEE International Conference on Multimedia and Expo, ICME 2007 | 0 | ||
13 | 2007 | Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction | Chen, Tai-Chen; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 13 | ||
14 | 2007 | An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing | Su, Bor-Yiing; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | ||
15 | 2007 | A Network-Flow-Based RDL Routing Algorithm for Flip-Chip Design | Fang, Jia-Wei; Lin, I-Jye; Chang, Yao-Wen ; Wang, Jyh-Herng | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
16 | 2007 | MB^*-Tree: A Multilevel Floorplanner for Large-Scale Building-Module Design | Lee, Hsun-Cheng; Chang, Yao-Wen ; Yang, Hannah Honghua | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
17 | 2006 | Inductance extraction for general interconnect structures | Lai, Chun-Ying; Jeng, Shyh-Kang ; Chang, Yao-Wen ; Tsai, Chia-Chun | International Symposium on Circuits and Systems, 2006. ISCAS '06 | 0 | 0 | |
18 | 2006 | Modern Floorplanning Based on B?-Tree and Fast Simulated Annealing | Chen, Tung-Chieh; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
19 | 2006 | A novel framework for multilevel full-chip gridless routing | Chen, Tai-Chen; Chang, Yao-Wen ; Lin, Shyh-Chang | Asia and South Pacific Conference on Design Automation, 2006. | 0 | 0 | |
20 | 2006 | RLC coupling-aware simulation and on-chip bus encoding for delay reduction | Tu, S.-W.; Jou, J.-Y.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 37 | 23 | |
21 | 2006 | Simultaneous block and I/O buffer floorplanning for flip-chip design | Peng, C.-Y.; Chao, W.-C.; Wang, J.-H.; YAO-WEN CHANG | Asia and South Pacific Design Automation Conference, ASP-DAC | 14 | ||
22 | 2006 | IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults | Li, K.S.-M.; Su, C.; Lee, C.-L.; Chen, J.E.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 11 | 9 | |
23 | 2006 | Placement of digital microfluidic biochips using the T-tree formuation | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen | 43rd annual Design Automation Conference | |||
24 | 2006 | Novel Full-Chip Gridless Routing Considering Double-Via Insertion | Chen, Huang-Yu; Chiang, Mei-Fang; Chang, Yao-Wen ; Chen, Lumdo; Han, Brian | ||||
25 | 2005 | 超大型?米積體電?無格線式全晶片繞線系統 (1/3) Gridless Full-Chip Routing for Very-Large Scale Nanometer ICs | 張耀文 | ||||
26 | 2005 | Crosstalk- and Performance-Driven Multilevel Full-Chip Routing | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, Der-Tsai | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
27 | 2005 | SoC test scheduling using the B*-tree based floorplanning technique | Wuu, Jen-Yi; Chen, Tung-Chieh; Chang, Yao-Wen | Asia and South Pacific Design Automation Conference, ASP-DAC 2005 | 0 | 0 | |
28 | 2005 | Reconfigurable platform for content science research | LIANG-GEE CHEN ; TEI-WEI KUO ; YAO-WEN CHANG ; SHAO-YI CHIEN ; CHIA-LIN YANG ; CHI-SHENG SHIH ; Ku, Mong-Kai | 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications | 0 | 0 | |
29 | 2005 | Multilevel full-chip routing for the X-based architecture | Ho, Tsung-Yi; Chang, Chen-Feng; Chang, Yao-Wen ; Chen, Sao-Jie | Design Automation Conference | |||
30 | 2005 | Multilevel routing with antenna avoidance | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie | Bulletin of the College of Engineering | |||
31 | 2005 | TCG: A transitive closure graph based representation for general floorplans | Lin, Jai-Ming; Chang, Yao-Wen | IEEE Transactions on | |||
32 | 2004 | Temporal floorplanning using the T-tree formulation | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen | IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004. | |||
33 | 2004 | Area, Delay, Power, and Noise Optimization for Transmission Lines | 張耀文 | ||||
34 | 2004 | Physical Design for Reconfigurable Computing System | 張耀文 | ||||
35 | 2004 | MR: A New Framework for Multilevel Full-Chip Routing | YAO-WEN CHANG ; Lin, Shih-Ping | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 40 | 34 | |
36 | 2004 | Simultaneous Floorplan and Buffer-Block Optimization | HUI-RU JIANG ; YAO-WEN CHANG ; Jou, Jing-Yang; Chao, Kai-Yuan | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 10 | 2 | |
37 | 2004 | Multilevel routing with jumper insertion for antenna avoidance | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie | IEEE International SOC Conference | 0 | 0 | |
38 | 2004 | Temporal Floorplanning Using 3D-subTCG | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen ; Chen, Hsin-Lung | Asia and South Pacific Design Automation Conference, ASP-DAC | |||
39 | 2004 | TCG-S: Orthogonal Coupling of P^*-Admissible Representations for General Floorplans | Lin, Jai-Ming; Chang, Yao-Wen | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | |||
40 | 2004 | A clustering- and probability-based approach for time-multiplexed FPGA partitioning | Wu, Guang-Ming; Chao, Mango Chia-Tso; YAO-WEN CHANG | Integration | 1 | 0 | |
41 | 2004 | Timing modeling and optimization under the transmission line model | Chen, Tai-Chen; Pan, Song-Ra; Chang, Yao-Wen | IEEE Transactions on | 32 | 27 | |
42 | 2003 | Area, Delay, Power , and Noise Optimization for Transmission Lines | 張耀文 | ||||
43 | 2003 | Physical Design for Reconfigurable Computing System | 張耀文 | ||||
44 | 2003 | Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme | Lin, Jai-Ming; YAO-WEN CHANG ; Lin, Shih-Ping | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 42 | 36 | |
45 | 2003 | A fast crosstalk- and performance-driven multilevel routing system | Ho, Tsung-Yi; Chang, Yao-Wen ; Chen, Sao-Jie ; Lee, D.T. | IEEE/ACM International Conference on Computer-Aided Design | 0 | 0 | |
46 | 2003 | Rectilinear block placement using B*-trees | Wu, G.-M.; Chang, Y.-C.; Chang, Y.-W.; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 25 | 21 | |
47 | 2003 | Inductance Modeling for On-Chip Interconnects | Tu, Shang-Wei; Shen, Wen-Zen; Chang, Yao-Wen ; Chen, Tai-Chen; Jou, Jing-Yang | Analog Integrated Circuits and Signal Processing | 5 | 4 | |
48 | 2002 | Performance Optimization Under the Transmission Line Model | 張耀文 | ||||
49 | 2002 | Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation | LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; YAO-WEN CHANG ; CHUNG-PING CHEN | VLSI Design | 4 | 2 | |
50 | 2002 | Comment on "Generic universal switch blocks" | Fan, Hongbing; Wu, Yu-Liang; Chang, Yao-Wen | IEEE Transactions on Computers | |||
51 | 2002 | Arbitrarily shaped rectilinear module placement using the transitive closure graph representation | Lin, J.-M.; Chen, H.-L.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | 8 | 9 | |
52 | 2002 | Performance-driven placement for dynamically reconfigurable FPGAs | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; Wu, Guang-Ming; Lin, Jai-Ming; Chang, Yao-Wen; YAO-WEN CHANG | ACM Transactions on Design Automation of Electronic Systems | 0 | 0 | |
53 | 2001 | Performance optimization by wire and buffer sizing under the transmission line model | Chen, Tai-Chen; Pan, Song-Ra; YAO-WEN CHANG | Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors | 3 | 0 | |
54 | 2001 | Generic ILP-based approaches for time-multiplexed FPGA partitioning | Wu, G.-M.; Lin, J.-M.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 30 | 22 | |
55 | 2001 | Matching-Based Algorithm for FPGA Channel Segmentation Design | YAO-WEN CHANG ; Lin, Jai-Ming; Wong, M. D. F. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 6 | 6 | |
56 | 2000 | Timing-driven routing for symmetrical-array-based FPGAs | CHANG, YAO-WEN ; ZHU, KAI; WONG, D. F. | ACM Transactions on Design Automation of Electronic Systems | |||
57 | 1999 | Generic universal switch blocks | Shyu, Michael; Chang, Yu-Dong; Wu, Guang-Ming; Chang, Yao-Wen; YAO-WEN CHANG | IEEE International Conference on Computer Design: VLSI in Computers and Processors | 1 | 0 |