第 1 到 42 筆結果,共 42 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2011 | Using SAT-based Craig interpolation to enlarge clock gating functions. | Lin, Ting-Hao; CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | |||
2 | 2011 | Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques | Wu, B.-H.; Yang, C.-J.; Tso, C.-C.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
3 | 2012 | Symbolic model checking on SystemC designs | Chou, C.-N.; Ho, Y.-S.; Hsieh, C.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | |||
4 | 2000 | Static property checking using ATPG vs. BDD techniques. | Huang, Chung-Yang; Yang, Bwolen; Tsai, Huan-Chih; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000 | |||
5 | 2010 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling | Kuen-Huei Lin; Siao-Jie Cai; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | |||
6 | 2008 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization | Kuen-Huei Lin; Siao-Jie Cai Huang; CHUNG-YANG HUANG | International SoC Design Conference (ISoCC) | |||
7 | 2011 | Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. | Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG | Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011 | |||
8 | 2011 | Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method | Yu-Fu Yeh; Chung-Yang (Ric) Huang; Chi-An Wu; Hsin-Cheng Lin; CHUNG-YANG HUANG | ACM/IEEE Design, Automation, and Test in Europe (DATE) conference | |||
9 | 1999 | Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
10 | 2011 | SoC HW/SW Verification and Validation | CHUNG-YANG HUANG ; Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 39 | 0 | |
11 | 2012 | A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints | Tsai, S.-H.; Li, M.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
12 | 2007 | Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving | Chih-Chun Lee; Jie-Hong R. Jiang; Chung-Yang Huang; Alan Mishchenko; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07) | |||
13 | 2009 | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique | Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang | Asia and South Pacific Design Automation Conference, 2009. ASP-DAC | 7 | 0 | |
14 | 2012 | A robust general constrained random pattern generator for constraints with variable ordering. | Wu, Bo-Han; CHUNG-YANG HUANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | |||
15 | 2013 | A robust constraint solving framework for multiple constraint sets in constrained random verification | Wu, B.-H.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | |||
16 | 2007 | QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure | Chi-An Wu; Ting-Hao Lin; Chih-Chun Lee; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | Design Automation and Test in Europe (DATE) Conference | |||
17 | 2012 | QuteRTL: Towards an open source framework for RTL design synthesis and verification | Yeh, H.-H.; Wu, C.-Y.; CHUNG-YANG HUANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | |||
18 | 2007 | QuteIP: An IP Qualification Framework for System on Chip | Hsing-Chih Hung; Chi-Wen Chang; Tin-Hao Lin; CHUNG-YANG HUANG | IEEE SoC Conference (SOCC) | |||
19 | 2011 | Property-specific sequential invariant extraction for SAT-based unbounded model checking | Yeh, H.-H.; Wu, C.-Y.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
20 | 2012 | Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. | Tang, Kai-Fu; Huang, Po-Kai; Chou, Chun-Nan; CHUNG-YANG HUANG | 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012 | |||
21 | 1998 | LIBRA - a library-independent framework for post-layout performance optimization. | Huang, Chung-Yang; Wang, Yucheng; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings of the 1998 International Symposium on Physical Design, ISPD 1998, Monterey, CA, USA, April 6-8, 1998 | |||
22 | 1998 | Libra - A Library-Independent Framework for Post-Layout Performance Optimization | R.C.-Y. Huang; Y. Wang; K.-T. Cheng; CHUNG-YANG HUANG | International Symposium on Physical Design | |||
23 | 2017 | Joint sequence learning and cross-modality convolution for 3D biomedical segmentation | Tseng K.-L.; Lin Y.-L.; Hsu W. ; WINSTON HSU ; CHUNG-YANG HUANG | 30th IEEE Conference on Computer Vision and Pattern Recognition | 123 | 0 | |
24 | 2011 | Interpolation-based incremental ECO synthesis for multi-error logic rectification. | Tang, Kai-Fu; Wu, Chi-An; Huang, Po-Kai; CHUNG-YANG HUANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | |||
25 | 2009 | Interpolant generation without constructing resolution graph. | Hsu, Chih-Jen; Huang, Shao-Lun; Wu, Chi-An; CHUNG-YANG HUANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 3 | 0 | |
26 | 2008 | Improving Constant-Coefficient Multiplier Verification by Partial Product Identification | Chao-Yue (Colby) Lai; CHUNG-YANG HUANG ; Kei-Yong Khoo | Design Automation and Test in Europe (DATE) | 6 | 0 | |
27 | 2010 | Formal Deadlock Checking on High-Level SystemC Designs | Chun-Nan Chou; Chang-Hong Hsu; Yueh-Tung Chao; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
28 | 2009 | A false-path aware formal static timing analyzer considering simultaneous input transitions. | Tsai, Shihheng; CHUNG-YANG HUANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | |||
29 | 2013 | A counterexample-guided interpolant generation algorithm for SAT-based model checking | Wu, C.-Y.; Wu, C.-A.; Lai, C.-Y.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | |||
30 | 2013 | Conquering the scheduling alternative explosion problem of SystemC symbolic simulation | Chou, C.-N.; Chu, C.-K.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | |||
31 | 2021 | Compatible Equivalence Checking of X-Valued Circuits | Wang Y.-N; Luo Y.-R; Chien P.-C; Wang P.-L; Wang H.-R; Lin W.-H; JIE-HONG JIANG ; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 0 | 0 | |
32 | 2010 | Automatic Constraint Generation for Guided Random Simulation | Hu-Hsi Yeh; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | |||
33 | 2016 | Automatic abstraction refinement of TR for PDR | Fan, K.; Yang, M.-J.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
34 | 2000 | Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. | Huang, Chung-Yang; Cheng, Kwang-Ting; CHUNG-YANG HUANG | Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000. | |||
35 | 2001 | An Analysis of ATPG and SAT algorithms for Formal Verification | G. Parthasarathy; K-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
36 | 2014 | Adaptive interpolation-based model checking | Lai, C.-Y.; Wu, C.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | |||
37 | 2010 | A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine | Chin-Chia Nien; Shih-Heng Tsai; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | |||
38 | 2010 | A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques | Bo-Han Wu; Chun-Ju Yang; Chung-Yang (Ric) Huang; Jie-Hong (Rol; ) Jiang; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM International Conference on Computer-Aided Design (ICCAD) | |||
39 | 2011 | A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization | Shao-Lun Huang; Chi-An Wu; Kai-Fu Tang; Chang-Hong Hsu; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 13 | 0 | |
40 | 1998 | A New Extended Finite State Machine (EFSM) Model for RTL Design Verification | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | |||
41 | 2009 | A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions | Shih-Heng Tsai; CHUNG-YANG HUANG | IEEE/ACM Design Automation Conference (DAC) | |||
42 | 2003 | A Circuit SAT Solver with Signal Correlation Guided Learning | Feng Lu; Li-C. Wang; K-T. Cheng; CHUNG-YANG HUANG | Design Automation & Test Conference |