第 1 到 3 筆結果,共 3 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
2 | 2020 | Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration | Jiang I.H.-R; Chang Y.-W; Huang J.-L; CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 5 | 0 | |
3 | 2002 | Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation | LEE, YU-MIN; CHEN, CHARLIE CHUNG-PING; YAO-WEN CHANG ; CHUNG-PING CHEN | VLSI Design | 4 | 2 |