https://scholars.lib.ntu.edu.tw/handle/123456789/309558
標題: | High-Performance VLSI Architecture of Adaptive Decision Feedback Equalizer Based on Predictive Parallel Branch Slicer (PPBS) Scheme | 作者: | AN-YEU(ANDY) WU Yang, M.-D. Wu, A.-Y. Lai, J.-T. AN-YEU(ANDY) WU |
公開日期: | 2004 | 卷: | 12 | 期: | 2 | 起(迄)頁: | 218-226 | 來源出版物: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-1642352711&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/309558 |
DOI: | 10.1109/TVLSI.2003.820521 |
顯示於: | 電機工程學系 |
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