https://scholars.lib.ntu.edu.tw/handle/123456789/427701
Title: | Joint AGC-Equalization (Joint AGC-EQ) Algorithm and VLSI Architecture For Wirelined Transceiver Designs | Authors: | Jyh-Ting Lai An-Yeu Wu Chien-Hsiung Lee AN-YEU(ANDY) WU |
Issue Date: | 2007 | Journal Volume: | 15 | Journal Issue: | 2 | Start page/Pages: | 997-1001 | Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems (Brief) | URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/427701 | DOI: | 10.1109/TVLSI.2007.893593 |
Appears in Collections: | 電機工程學系 |
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