公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2023 | A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit with a Single Inductor for Piezoelectric Energy Harvesting | Chen, Chi Wei; Pranoto, Weining Zeng; HSIN-SHU CHEN ; WEN-JONG WU | IEEE Transactions on Power Electronics | 0 | | |
2018 | A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting | Kai-Ren Cheng; Hsin-Shu Chen; Micka?l Lallart; Wen-Jong Wu; HSIN-SHU CHEN | IEEE ISCAS | 6 | 0 | |
2019 | A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System | Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Journal of Solid-State Circuits | 4 | 5 | |
2018 | A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System | Yao-Sheng Hu; Li-Yu Huang; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Asian Solid-State Circuit Conference | 1 | 0 | |
2017 | A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC | Hu, Y.-S.; Huang, P.-C.; Yang, M.-T.; Wu, S.-W.; HSIN-SHU CHEN | 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings | | | |
2009 | A 1-GS/s 6-bit Two-Channel Two-Step ADC in 0.13-um CMOS | Hung-Wei Chen; I-Ching Chen; Huan-Chieh Tseng; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Journal of Solid-State Circuits | 14 | 10 | |
2006 | A 1.5-V 10-ppm//spl deg/C 2nd-order curvature-compensated CMOS bandgap reference with trimming | Hsiao, Sen-Wen; Huang, Yen-Chih; Liang, David; Chen, H.W.K.; Chen, Hsin-Shu | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2006 | A 1.5-V 10-ppm/°C 2nd-order curvature-compensated CMOS bandgap reference with trimming | Hsiao, S.-W.; Huang, Y.-C.; Liang, D.; Chen, H.-W.K.; HSIN-SHU CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2013 | A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC | Chien-Jian Tseng; Yi-Chun Hsieh; Ching-Hua Yang; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Transactions on Circuits and Systems I | 13 | 10 | |
2021 | A 10-bit 300 MS/s pipeline ADC with time-domain MDAC | Chen H.-S; Tseng C.-J; Chuang Y.-W; Chang C.-W.; HSIN-SHU CHEN | Analog Integrated Circuits and Signal Processing | | | |
2012 | A 10-bit 320MS/s Stage-Gain-Error Self-Calibration Pipeline ADC | Chien-Jian Tseng; Hung-Wei Chen; Wei-Ting Shen; Wei-Chih Cheng; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Journal of Solid-State Circuits | 19 | 18 | |
2014 | 11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS | Tai, H.-Y.; Hu, Y.-S.; Chen, H.-W.; HSIN-SHU CHEN | IEEE International Solid-State Circuits Conference | | | |
2017 | A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape technique | Hu, Y.-S.; Lin, K.-Y.; HSIN-SHU CHEN | 2016 IEEE Asian Solid-State Circuits Conference, A-SSCC 2016 - Proceedings | | | |
2016 | A 12.5fJ/conversion-step 8-bit 800 MS/s Two-Step SAR ADC | Yao-Sheng Hu; Po-Chao Huang; Hung-Yen Tai; HSIN-SHU CHEN | IEEE Transactions on Circuits and Systems II | 6 | 7 | |
2001 | A 14b 20MSamples/s CMOS Pipelined ADC | Hsin-Shu Chen; Bang-Sup Song; Kantilal Bacrania; HSIN-SHU CHEN | IEEE Journal of Solid-State Circuits | 52 | 36 | |
2021 | A 34.3?dB SNDR, 2.3GS/s, Sub-radix pipeline ADC using incomplete settling technique with background radix detector | Chen H.-S; Tseng C.-J; Chen C.-M; Chen H.-W.; HSIN-SHU CHEN | Analog Integrated Circuits and Signal Processing | | | |
2017 | A 510nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-Switching Technique | Yao-Sheng Hu; Kai-Yue Lin; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Dig. Symp. VLSI Circuits | 10 | 0 | |
2016 | An 8-bit 900MS/S two-step SAR ADC | Huang, P.-C.; Hu, Y.-S.; Tai, H.-Y.; HSIN-SHU CHEN | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2018 | An 89.55dB-SFDR 179.6dB-FoM s 12-bit lMS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration | Hu Y.-S; Lin J.-H; Lin D.-G; Lin K.-Y; HSIN-SHU CHEN | 2018 IEEE Asian Solid-State Circuits Conference, A-SSCC 2018 - Proceedings | | | |
2018 | An 89.55dB-SFDR 179.6dB-FoMS 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration | Yao-Sheng Hu; Jhao-Huei Lin; Ding-Guo Lin; Kai-Yue Lin; Hsin-Shu Chen; HSIN-SHU CHEN | IEEE Asian Solid-State Circuit Conference | 0 | 0 | |