公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
0 | a | a; AN-YEU(ANDY) WU ; 吳安宇 | | | | |
2007 | A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Yu, C.; Chen, J.; Wu, A.-Y.; AN-YEU(ANDY) WU | 2007 IEEE Asian Solid-State Circuits Conference | | | |
2011 | A 0.16nJ/bit/iteration 3.38mm 2 turbo decoder chip for WiMAX/LTE standards | AN-YEU(ANDY) WU ; Lin, C.-H.; Chen, C.-Y.; Chang, E.-J.; AN-YEU(ANDY) WU | 2011 International Symposium on Integrated Circuits | | | |
2015 | A 1.96 mm 2 low-latency multi-mode crypto-coprocessor for PKC-based IoT security protocols | CHEN-MOU CHENG ; AN-YEU(ANDY) WU ; CR Tsai; MC Hsiao; WC Shen; AYA Wu; CHEN-MOU CHENG ; AN-YEU(ANDY) WU | 2015 IEEE International Symposium on Circuits and Systems (ISCAS) | | | |
2007 | A 19-mode 8.29mm2 52-mW LDPC decoder chip for IEEE 802.16e system | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE Symposium on VLSI Circuits | | | |
2010 | A 2.17 mm2 125 mW reconfigurable SVD chip for IEEE 802.11n system | AN-YEU(ANDY) WU ; Chen, Y.-L.; Jheng, T.-J.; Zhan, C.-Z.; AN-YEU(ANDY) WU | ESSCIRC 2010 - 36th European Solid State Circuits Conference | | | |
2005 | A 2gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chang, L.-H.; Chen, Y.-G.; Chang, S.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2009 | A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; Lin, C.-H.; AN-YEU(ANDY) WU | Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2008 | A 7.39mm2 76mw (1944, 972) LDPC decoder chip for IEEE 802.11n applications | AN-YEU(ANDY) WU ; Shih, X.-Y.; Zhan, C.-Z.; AN-YEU(ANDY) WU | 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 | | | |
2009 | A channel-adaptive early termination strategy for LDPC decoders | AN-YEU(ANDY) WU ; Chen, Y.-H.; Chen, Y.-J.; Shih, X.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
2007 | A clock-fault tolerant architecture and circuit for reliable nanoelectronics system | AN-YEU(ANDY) WU ; Ang, W.T.; Rao, H.F.; Yu, C.; Liu, J.; Wey, I.-C.; Wu, A.-Y.; Zhao, H.; Chen, J.; AN-YEU(ANDY) WU | 2007 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2007 | | | |
2004 | A design flow for multiplierless linear-phase fir filters: From system specification to verilog code | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Jou, S.-J.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2005 | A DVB-T baseband demodulator design based on multimode silicon IPs | AN-YEU(ANDY) WU ; Jheng, K.-Y.; Wu, T.-H.; Wang, Y.-C.; Yeo, J.-C.; Cho, Y.-J.; AN-YEU(ANDY) WU | 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test | | | |
2004 | A fast and power-saving self-timed manchester carry-bypass adder for booth multiplier-accumulator design | AN-YEU(ANDY) WU ; Wey, I.-C.; Chow, H.-C.; Chen, Y.-G.; AN-YEU(ANDY) WU | 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits | | | |
2003 | A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
2005 | A high-speed scalable shift-register based on-chip serial communication design for SoC applications | AN-YEU(ANDY) WU ; Wey, I.-C.; Chen, Y.-G.; Wu, C.-T.; Wang, W.; AN-YEU(ANDY) WU | 2005 PhD Research in Microelectronics and Electronics | | | |
2006 | A low cost packet detector in OFDM-based ultra-wideband systems | AN-YEU(ANDY) WU ; Lai, J.-T.; Chu, N.-Y.; Wu, A.-Y.; Chen, W.-C.; AN-YEU(ANDY) WU | 2006 IEEE Workshop on Signal Processing Systems Design and Implementation | | | |
2012 | A low-complexity grouping FFT-based codebook searching algorithm in LTE system | AN-YEU(ANDY) WU ; Lin, Y.-H.; Zhan, C.-Z.; Chu, C.-Y.; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
2005 | A memory-reduced Log-MAP kernel for turbo decoder | AN-YEU(ANDY) WU ; Tsai, T.-H.; Lin, C.-H.; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
2007 | A new binomial mapping and optimization algorithm for reduced-complexity mesh-based on-chip network | AN-YEU(ANDY) WU ; Shen, W.-T.; Chao, C.-H.; Lien, Y.-K.; AN-YEU(ANDY) WU | NOCS 2007: First International Symposium on Networks-on-Chip | | | |