Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
2001 | An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA | | | |
2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
2010 | Power supply noise reduction in broadcast-based compression environment for at-speed scan testing | C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2003 | Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II | 29 | 24 | |
2003 | Practical Considerations in Applying-Modulation-Based Analog BIST to Sampled-Data Systems | Hong, Hao-Chiao; Huang, Jiun-Lang ; Cheng, Kwang-Ting; Wu, Cheng-Wen; Kwai, Ding-Ming | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | | | |
2005 | Random jitter testing using low tap-count delay lines | JIUN-LANG HUANG | Asian Test Symposium | | | |
2008 | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | International Test Conference | 48 | 0 | |
2019 | Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test | Chen, C.-Y.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2010 | A robust ADC code hit counting technique | Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | | | |
2010 | A robust ADC code hit counting technique. | Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG | Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010 | | | |
2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2000 | A sigma-delta modulation based BIST scheme for mixed-signal circuits | JIUN-LANG HUANG ; Cheng, K.-T. | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 27 | 0 | |
2011 | Sigma-delta modulation based wafer-level testing for TFT-LCD source driver ICs | W.-A. Lin; C.-C. Li; J.-L. Huang; JIUN-LANG HUANG | VLSI Test Symposium | 1 | 0 | |
2008 | Software-Based Self-Testing | Huang, J.-L.; Tim, K.-T.; JIUN-LANG HUANG | System-on-Chip Test Architectures | | | |
2017 | Source code transformation for software-based on-line error detection | T.-Y. Tsai; J.-L. Huang; JIUN-LANG HUANG | IEEE Conference on Dependable and Secure Computing | 3 | 0 | |
1999 | Specification Back-Propagation and Its Application to DC Fault Simulation for Analog/Mixed-Signal Circuits. | Huang, Jiun-Lang; Pan, Chen-Yang; Cheng, Kwang-Ting; JIUN-LANG HUANG | 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA | | | |