公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2010 | A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine | Cheng, C.-C.; Tsai, Y.-M.; Chen, L.-G.; Ch; rakasan, A.P.; LIANG-GEE CHEN | Custom Integrated Circuits Conference | 7 | 0 | |
2012 | A 1.0TOPS/W 36-core neocortical computing processor with 2.3Tb/s Kautz NoC for universal visual recognition | Tsai, C.-Y.; Lee, Y.-J.; Chen, C.-T.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Solid-State Circuits Conference | 6 | 0 | |
2008 | A 100 MHZ 1920×1080 HD-photo 20 frames/sec JPEG XR encoder design | Chien, C.-Y.; Huang, S.-C.; Lin, S.-H.; Huang, Y.-C.; Chen, Y.-C.; Chou, L.-C.; Chuang, T.-D.; Chang, Y.-W.; Pan, C.-H.; Chen, L.-G.; LIANG-GEE CHEN | International Conference on Image Processing, ICIP | 3 | 0 | |
2013 | A 1062Mpixels/s 8192×4320p High Efficiency Video Coding (H.265) encoder chip | Tsai, S.-F.; Li, C.-T.; Chen, H.-H.; Tsung, P.-K.; Chen, K.-Y.; Chen, L.-G.; LIANG-GEE CHEN | IEEE Symposium on VLSI Circuits | | | |
2015 | A 130.3 mW 16-core mobile GPU with power-aware pixel approximation techniques | Chen, Y.-J.; Hsu, C.-H.; Hung, C.-Y.; Chang, C.-M.; Chuang, S.-Y.; Chen, L.-G.; Chien, S.-Y.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE Journal of Solid-State Circuits | 5 | 3 | |
2013 | A 130.3mW 16-core mobile GPU with power-aware approximation techniques | Chen, Y.-J.; Chuang, S.-Y.; Hung, C.-Y.; Hsu, C.-H.; Chang, C.-M.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 | 5 | 0 | |
2011 | A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications | Chang, C.-M.; Chen, Y.-J.; Lu, Y.-C.; Lin, C.-Y.; Chen, L.-G.; Chien, S.-Y.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE Asian Solid-State Circuits Conference, A-SSCC 2011 | 7 | 0 | |
2015 | A 1920×1080 30fps 611 mW five-view depth-estimation processor for light-field applications | Chen, H.-H.; Huang, C.-T.; Wu, S.-S.; Hung, C.-L.; Ma, T.-C.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Solid-State Circuits Conference | 16 | 0 | |
2010 | A 212 MPixels/s 4096 × 2160p multiview video encoder chip for 3D/Quad full HDTV applications | Ding, L.-F.; Chen, W.-Y.; Tsung, P.-K.; Chuang, T.-D.; Hsiao, P.-H.; Chen, Y.-H.; Chiu, H.-K.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE Journal of Solid-State Circuits | 50 | 40 | |
2008 | A 26mW 6.4GFLOPS multi-core stream processor for mobile multimedia applications | Tsao, Y.-M.; Sun, C.-H.; Lin, Y.-C.; Lok, K.-H.; Hsu, C.-J.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; |SHAO-YI CHIEN | IEEE Symposium on VLSI Circuits | 3 | 0 | |
2013 | A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation | Tsai, Y.-M.; Yang, T.-J.; Chen, L.-G.; LIANG-GEE CHEN | IEEE Symposium on VLSI Circuits | | | |
2006 | A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications | Lin, C.-P.; Tseng, P.-C.; Chiu, Y.-T.; Lin, S.-S.; Cheng, C.-C.; Fang, H.-C.; Chao, W.-M.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Solid-State Circuits Conference | | | |
1997 | A bit-level pipelined VLSI architecture for the running order algorithm | Chen, C.-T.; Chen, L.-G.; Hsiao, J.-H.; LIANG-GEE CHEN | IEEE Transactions on Signal Processing | 4 | 2 | |
1998 | A block shifting method for reduction of blocking effects in subband/wavelet image coding | Wu, P.-C.; Chen, L.-G.; Lai, Y.-K.; LIANG-GEE CHEN | IEEE Transactions on Consumer Electronics | 1 | 1 | |
2009 | A branch selection multi-symbol high throughput CABAC decoder architecture for H.264/AVC | Lin, P.-C.; Chuang, T.-D.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Symposium on Circuits and Systems | 16 | 0 | |
2012 | A chip architecture for compressive sensing based detection of IC trojans | Tsai, Y.-M.; Huang, K.-Y.; Kung, H.T.; Vlah, D.; Gwon, Y.L.; Chen, L.-G.; LIANG-GEE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 3 | 0 | |
2008 | A cost effective reconfigurable memory for multimedia multithreading streaming architecture | Tsao, Y.-M.; Lok, K.-H.; Lin, Y.-C.; Sun, C.-H.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | 0 | 0 | |
2001 | A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core | Tsai, T.-H.; Wu, R.-J.; Chen, L.-G.; LIANG-GEE CHEN | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology | 0 | 0 | |
2007 | A cost-efficient residual prediction VLSI architecture for H. 264/AVC scalable extension | Chen, Y.-H.; Chuang, T.-D.; Tsai, C.-Y.; Chen, Y.-J.; Chen, L.-G.; LIANG-GEE CHEN | 26th Picture Coding Symposium | | | |
1998 | A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm | Lai, Y.-K.; Chen, L.-G.; LIANG-GEE CHEN | IEEE Transactions on Circuits and Systems for Video Technology | 66 | 59 | |