https://scholars.lib.ntu.edu.tw/handle/123456789/387274
Title: | A fully parallel ldpc decoder architecture using probabilistic min-sum algorithm for high-throughput applications | Authors: | CHIA-HSIANG YANG Cheng, C.-C. Yang, J.-D. Lee, H.-C. Yang, C.-H. Ueng, Y.-L. CHIA-HSIANG YANG |
Issue Date: | 2014 | Journal Volume: | 61 | Journal Issue: | 9 | Start page/Pages: | 2738-2746 | Source: | IEEE Transactions on Circuits and Systems I: Regular Papers | URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84906951064&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/387274 |
DOI: | 10.1109/TCSI.2014.2312479 |
Appears in Collections: | 電機工程學系 |
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