https://scholars.lib.ntu.edu.tw/handle/123456789/497778
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Jiang, J.H. | en_US |
dc.contributor.author | Devadas, S. | en_US |
dc.contributor.author | JIE-HONG JIANG | en_US |
dc.creator | Jiang, J.H.;Devadas, S. | - |
dc.date.accessioned | 2020-06-11T06:11:12Z | - |
dc.date.available | 2020-06-11T06:11:12Z | - |
dc.date.issued | 2009 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/497778 | - |
dc.relation.ispartof | Electronic Design Automation | - |
dc.title | Logic Synthesis in a Nutshell | en_US |
dc.type | book chapter | en |
dc.identifier.doi | 10.1016/B978-0-12-374364-0.50013-8 | - |
dc.identifier.scopus | 2-s2.0-84882815173 | - |
dc.identifier.url | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84882815173&doi=10.1016%2fB978-0-12-374364-0.50013-8&partnerID=40&md5=4c4ad3308eac56e55d1b751d270bf8fd | - |
dc.relation.pages | 299-404 | - |
item.openairecristype | http://purl.org/coar/resource_type/c_18cf | - |
item.openairetype | book chapter | - |
item.grantfulltext | none | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.orcid | 0000-0002-2279-4732 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
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