| Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
| 2016 | VCR: Simultaneous via-template and cut-template-aware routing for directed self-assembly technology | Su, Y.-H.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | 4 | 0 | |
| 1996 | A velocity-overshoot capacitance model for 0.1 μm MOS transistors | Kuo, J.B.; Chang, Y.W.; Lai, C.S.; YAO-WEN CHANG | Solid-State Electronics | 4 | 4 | |
| 2022 | Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures | Wen H; Cai Y; Hsu Y; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 0 | |
| 2020 | Via-based redistribution layer routing for InFO packages with irregular pad structures | Wen, H.-T.; Cai, Y.-J.; Hsu, Y.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 7 | 0 | |
| 2021 | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units | Chou Y; Hsu J.-W; Chen T.-C.; YAO-WEN CHANG | Proceedings - Design Automation Conference | 3 | 0 | |
| 2006 | Voltage Island aware floorplanning for power and timing optimization | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 74 | 0 | |
| 2006 | Voltage island aware floorplanning for power and timing optimization. | Lee, Wan-Ping; Liu, Hung-Yi; Chang, Yao-Wen; YAO-WEN CHANG | 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006 | 0 | 0 | |
| 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE/ACM International Conference on Computer-Aided Design | 4 | | |
| 2011 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs | Chuang, Y.-L.; Lee, P.-W.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 3 | |
| 2009 | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Chuang, Yi-Lin; Lee, Po-Wei; Chang, Yao-Wen; YAO-WEN CHANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 4 | 0 | |
| 2009 | Voltage-island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 14 | 11 | |
| 2009 | Voltage-Island partitioning and floorplanning under timing constraints | Lee, W.-P.; Liu, H.-Y.; Chang, Y.-W.; YAO-WEN CHANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1 | 11 | |
| 2022 | Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification | Bai X; Zhu Z; Zou P; Chen J; Yu J; YAO-WEN CHANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | 0 | 0 | |
| 2018 | WB-trees: A meshed tree representation for FinFET analog layout designs | Lu, Y.-S.; Chang, Y.-H.; Chang, Y.-W. | Design Automation Conference | 7 | 0 | |
| 2007 | X-architecture placement based on effective wire models | Chen, T.-C.; Chuang, Y.-L.; Chang, Y.-W.; YAO-WEN CHANG | International Symposium on Physical Design | 1 | 0 | |
| 2007 | X-route: An x-architecture full-chip multilevel router | Chang, C.-F.; Chang, Y.-W.; YAO-WEN CHANG | 20th Anniversary IEEE International SOC Conference | 4 | 0 | |
| 2022 | Y-architecture-based flip-chip routing with dynamic programming-based bend minimization | Nie, Szu Ru; Chen, Yen Ting; YAO-WEN CHANG | Proceedings - Design Automation Conference | 1 | | |
| 2008 | 兆級晶片系統前瞻技術研究－子計畫六：兆級晶片系統實體整合之研究(2/3) | 張耀文 | | | |  |
| 2007 | 兆級晶片系統前瞻技術研究－子計畫六：兆級晶片系統實體整合之研究(3/3) | 張耀文 | | | | |
| 2005 | 多媒體通訊系統中可重組化運算技術之研究─子計畫五：可重組化系統之實體設計(3/3) | 張耀文 | | | | |
