公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 | |
2009 | Ch. 8 Logic and Circuit Simulation | J.-L. Huang; C.-K. Koh; S. F. Cauley; JIUN-LANG HUANG | Electronic Design Automation: Synthesis, Verification, and Test | | | |
2007 | Chap. 11 Software-Based Self-Testing | J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | System on Chip Test Architectures | | | |
2006 | Chap. 3: Logic and Fault Simulation | J.-L. Huang; James C.-M. Li; Duncan M. (Hank) Walker; JIUN-LANG HUANG | VLSI Test Principles and Architectures | | | |
2000 | Characterization of a pseudo-random testing technique for analog and mixed-signal built-in-self-test | Tofte, Jan Arild; Ong, Chee-Kian; JIUN-LANG HUANG ; Cheng, Kwang-Ting | Proceedings of the IEEE VLSI Test Symposium | | | |
2000 | Characterization of a Pseudo-Random Testing Technique for Analog and Mixed-Signal Built-in-Self-Test. | Tofte, Jan Arild; Ong, Chee-Kian; Huang, Jiun-Lang; Cheng, Kwang-Ting (Tim); JIUN-LANG HUANG | 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada | | | |
2009 | Characterizing Integrator Leakage of Single-Bit DS Modulator Using DC Input | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automatic Conference | | | |
2009 | A Charge-Sensing-Capable Source Driver for TFT Array Testing in System-on-Panel Displays. | Lin, Chen-Wei; JIUN-LANG HUANG | JCP | | | |
2011 | Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | International Test Conference | 3 | 0 | |
2009 | Co-Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADC | X.-L. Huang; Yuan-Chi Yu; Jiun-Lang Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 1 | 0 | |
2018 | Conference Reports: Report on 2017 IEEE Asian Test Symposium | Li, Jin-Fu; JIUN-LANG HUANG | IEEE Design and Test | 0 | 0 | |
2016 | CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator | K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 1 | 1 | |
2010 | CSER: BISER-based concurrent soft-error resilience | CHIEN-MO LI ; JIUN-LANG HUANG ; Laung-Terng Wang; Touba, N.A.; Zhigang Jiang; Shianling Wu; Jiun-Lang Huang; CHIEN-MO LI ; JIUN-LANG HUANG | VLSI Test Symposium (VTS) | | | |
2000 | A delta-sigma modulation based BIST scheme for mixed-signal systems | Huang, J.-L.; Cheng, K.-T.; JIUN-LANG HUANG | 2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000 | | | |
2017 | Design and implementation of an EG-pool based FPGA formatter with temperature compensation | Y.-K. Huang; K.-T. Li; C.-L. Hsiao; C.-A. Lee; J.-L. Huang; T. Kuo; JIUN-LANG HUANG | Asian Test Symposium | 2 | 0 | |
2018 | Design and Implementation of an FPGA-Based 16-Channel Data/Timing Formatter | Hou, G.-H.; Huang, W.-C.; Huang, J.-L.; Kuo, T.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2015 | Design and Implementation of an FPGA-Based Data/Timing Formatter | Y.-Y. Chen; J.-L. Huang; T. Kuo; X.-L. Huang; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 6 | 6 | |
2008 | Design of a Fault Tolerant Carry Lookahead Adder | C.-Y. Huang, T.-H. Ko; J.-L. Huang; JIUN-LANG HUANG | International Test Synthesis Workshop | | | |
2015 | Design, automation, and test for low-power and reliable flexible electronics | T.-C. Huang; JIUN-LANG HUANG ; K.-T. Cheng | Foundations and Trends in Electronic Design Automation | 10 | 0 | |
2009 | Diagnosing integrator leakage of single-bit first-order Δσ modulator using DC input | Huang, X.-L.; Yang, C.-Y.; JIUN-LANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | | | |