公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2013 | On guaranteeing capture safety in at-speed scan testing with broadcast-scan-based test compression | K. Enokimoto; X. Wen; K. Miyase; J.-L. Huang; S. Kajihara; L.-T. Wang; JIUN-LANG HUANG | International Conference on VLSI Design | 5 | 0 | |
2008 | On optimizing fault coverage, pattern count, and ATPG run time using a hybrid single-capture scheme for testing scan designs | Wu, S.; Wang, L.-T.; Jiang, Z.; Song, J.; Sheu, B.; Wen, X.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; CHIEN-MO LI ; JIUN-LANG HUANG | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems | 1 | 0 | |
2011 | On pre/post-bond testing and calibrating SAR ADC array in 3-D CMOS imager | Huang, X.-L.; Kang, P.-Y.; Huang, J.-L.; Chou, Y.-F.; Lee, Y.-P.; Kwai, D.-M.; JIUN-LANG HUANG | Proceedings - 2011 IEEE 17th International Mixed-Signals, Sensors and Systems Test Workshop, IMS3TW 2011 | | | |
2002 | On-Chip Analog Response Extraction with 1-Bit Sigma-Delta Modulators | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; JIUN-LANG HUANG | Asian Test Symposium | 11 | 0 | |
2006 | On-chip random jitter testing using low tap-count coarse delay lines | JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications (JETTA) | 2 | 1 | |
2001 | An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. | Huang, Jiun-Lang; Cheng, Kwang-Ting; JIUN-LANG HUANG | 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA, USA | | | |
2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
2008 | PHS-Fill: A Low Power Supply Noise Test Pattern Generation Technique for At-Speed Testing in Huffman Coding Test Compression Environment | Y.-T. Lin; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 3 | 0 | |
2009 | Power Supply Noise Reduction for At-Speed Scan Testing in Linear-Decompression Environment | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | IEEE Transactions on Compuuter-Aided Design | 16 | 9 | |
2010 | Power supply noise reduction in broadcast-based compression environment for at-speed scan testing | C.-Y. Liang; M.-F. Wu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |
2003 | Practical Considerations in Applying Sigma-Delta Modulation-Based Analog BIST to Sampled-Data Systems | H. C. Hong; J. L. Huang; K. T. Cheng; C. W. Wu; D. M. Kwai; JIUN-LANG HUANG | IEEE Transactions on Circuits and Systems II | 29 | 24 | |
2003 | Practical Considerations in Applying-Modulation-Based Analog BIST to Sampled-Data Systems | Hong, Hao-Chiao; Huang, Jiun-Lang ; Cheng, Kwang-Ting; Wu, Cheng-Wen; Kwai, Ding-Ming | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
2012 | Pre-bond characterization of 1-bit/stage pipelined ADC for 3D-IC applications | Y.-H. Chou; J.-L. Huang; X.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | | | |
2005 | Random jitter testing using low tap-count delay lines | JIUN-LANG HUANG | Asian Test Symposium | | | |
2008 | Reducing Power Supply Noise in Linear-Decompressor-Based Test Data Compression Environment for At-Speed Testing | M.-F. Wu; J.-L. Huang; X. Wen; K. Miyase; JIUN-LANG HUANG | International Test Conference | 48 | 0 | |
2019 | Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test | Chen, C.-Y.; JIUN-LANG HUANG | Proceedings of the Asian Test Symposium | | | |
2010 | A robust ADC code hit counting technique | Huang, J.-L.; Chou, K.-Y.; Lu, M.-H.; Huang, X.-L.; JIUN-LANG HUANG | Proceedings -Design, Automation and Test in Europe, DATE | | | |
2010 | A robust ADC code hit counting technique. | Huang, Jiun-Lang; Chou, Kuo-Yu; Lu, Ming-Huan; Huang, Xuan-Lun; JIUN-LANG HUANG | Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010 | | | |
2011 | Robust Circuit Design for Flexible Electronics | T.-C Huang; J.-L. Huang; K.-T. Cheng; JIUN-LANG HUANG | IEEE Design & Test of Computers | 13 | 10 | |
2015 | SDC-TPG: A deterministic zero-inflation parallel test pattern generator | C.-H. Chang; K.-W. Yeh; J.-L. Huang; L.-T. Wang; JIUN-LANG HUANG | Asian Test Symposium | 4 | 0 | |