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Showing results 135 to 154 of 225
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Issue Date
Title
Author(s)
Source
scopus
WOS
Fulltext/Archive link
2014
Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC
G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
Asia Pacific CSEE Conference
1994
Low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers
Wang, J.Y.; Chen, Y.G.; KuoJB
Electronics Letters
1
0
1999
Low-Voltage CMOS VLSI Circuits
J. B. Kuo; J. H. Lou; JAMES-B KUO
2001
Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques
J. B. Kuo; S. C. Liu; JAMES-B KUO
2007
Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic
E. K. Loo; J. B. Kuo; M. Syrzycki; JAMES-B KUO
Canadian Conference on Electrical and Computer Engineering
2010
Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications
W.C.H. Lin; J. B. Kuo; JAMES-B KUO
ISCAS
0
0
2001
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2004
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2013
Modeling Advanced PD SOI CMOS Devices
JAMES-B KUO
NSC Seminar
2012
Modeling Hot-Carrier-Induced Reliability of Poly-silicon Thin Film Transistors
L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO
IEEE International Conference on Electron Devices and Solid State Circuit
0
0
2018
Modeling of Breakdown Voltage for SOI Trench LDMOS Device Based on Conformal Mapping
Wang Y; Wang Z; Bai T; JAMES-B KUO
IEEE Transactions on Electron Devices
1999
Modeling of Deep-Submicron SOI CMOS VLSI Devices
JAMES-B KUO
National Science Council Monthly
2001
Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model
J. B. Kuo; S. C. Lin; JAMES-B KUO
International Conference on Semiconductor IC Technology (ICSICT)
1
0
2018
Modeling power vertical high-k MOS device with interface charges via superposition methodology-breakdown voltage and specific ON-resistance
Wang Z; Wang X; JAMES-B KUO
IEEE Transactions on Electron Devices
2007
Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Top/Bottom Gate
C. H. Hsu; J. B. Kuo; JAMES-B KUO
Electron Devices and Solid State State Circuits (EDSSC) Conf
0
0
2010
Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach
J. S. Su; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
EUROSOI
2009
Modeling the Floating-Body-Effect-Induced Drain Current Behavior of PD SOI NMOS Device Via SPICE BJT/MOS Model Approach
J. S. Su; J. B. Kuo; JAMES-B KUO
Compact TFT Modeling Workshop
0
0
2011
Modeling the Floating-Body-Effect-Related Transient Behavior of 40nm PD SOI NMOS Device via the SPICE Bipolar/MOS Model
S. W. Fang; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
International Semiconductor Device Research Symposium ISDRS
1
0
2003
Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure
S. C. Lin; J. B. Kuo; JAMES-B KUO
IEEE Transactions on Electron Devices
74
64
2007
Modeling the Gate Tunneling Current Effects of Sub-100nm NMOS Devices with an Ultra-thin (1nm) Gate Oxide
JAMES-B KUO
International Electron devices Semiconductor Technology Conf (IEDST)