公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2014 | A 3-25 Gb/s four-channel receiver with noise-canceling TIA and power-scalable sLA | Chien, Y.-H.; Fu, K.-L.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 21 | 21 | |
2016 | A 3.2GHz digital phase-locked loop with background supply-noise cancellation | Yeh, C.-W.; Hsieh, C.-E.; Liu, S.-I.; SHEN-IUAN LIU | Digest of Technical Papers - IEEE International Solid-State Circuits Conference | 22 | 0 | |
2008 | 3.5mW W-band frequency divider with wide locking range in 90nm CMOS technology | Kun-Hung Tsai; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu; SHEN-IUAN LIU | International Solid-State Circuits Conference | 50 | 0 | |
2012 | A 3.6 mW 125.7-131.9 GHz divide-by-4 injection-locked frequency divider in 90 nm CMOS | Lee, I.-T.; Wang, C.-H.; Ko, C.-L.; Juang, Y.-Z.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Microwave and Wireless Components Letters | 1 | 1 | |
2011 | 3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS | I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 9 | 0 | |
2009 | A 33.6-to-33.8 Gb/s burst-mode CDR in 90 nm CMOS technology | Cho, L.-C.; Lee, C.; Hung, C.-C.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 8 | 6 | |
2002 | 38-GHz無線收發系統關鍵元組件技術(1/3)子計畫七:射頻頻率合成器與放大器晶片設計(1/3) | 劉深淵 | | | | |
2003 | 38-GHz無線收發系統關鍵元組件技術─子計畫七:射頻頻率合成器與放大器晶片設計(2/3) | 劉深淵 | | | | |
2013 | 4-Gb/s parallel receivers with adaptive far-end crosstalk cancellation | Yan-Yu Lin; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 3 | 2 | |
2013 | 4-Gb/s parallel receivers with adaptive FEXT cancellation by pulse-width and amplitude calibrations | Yan-Yu Lin; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 1 | 1 | |
2008 | 40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS | Chih-Fan Liao; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 88 | 78 | |
2017 | A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis | Su, W.-J.; Liu, S.-I.; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems I: Regular Papers | 11 | 10 | |
2015 | A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting | Lin, Y.-F.; Huang, C.-C.; Lee, J.-Y.M.; Chang, C.-T.; Liu, S.-I.; SHEN-IUAN LIU | Proceedings - 2014 IEEE Asian Solid-State Circuits Conference, A-SSCC 2014 | 9 | 0 | |
2006 | 5-bit, 10 GSamples/s track-and-hold circuit with input feedthrough cancellation | I-HSIANG WANG ; Lin, J.-L.; SHEN-IUAN LIU | Electronics Letters | 15 | 9 | |
2021 | A 5-Gb/s Adaptive Digital CDR Circuit with SSC Capability and Enhanced High-Frequency Jitter Tolerance | Chang S.-C; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 3 | 3 | |
2004 | 5.8-/5.2-/2.4-GHz SiGe LC VCO with Wide Tuning Range | Chun-Yi Kuo; Che-Fu Liang; Shen-Iuan Liu; SHEN-IUAN LIU | 2004 VLSI/CAD Symposium | | | |
2020 | A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT | Chang M.-C; Wu M.-H; SHEN-IUAN LIU | 2020 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2020 | 1 | 0 | |
2017 | A 56Gbps PAM-4 optical receiver front-end | Fu, K.-L.; Liu, S.-I.; SHEN-IUAN LIU | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Proceedings | 7 | 0 | |
2002 | A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay | Chang, Hsiang-Hui; Lin, Jyh-Woei; Liu, Shen-Iuan | Custom Integrated Circuits Conference, 2002 | 0 | 0 | |
2016 | A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS | Hsieh, M.-H.; Chen, L.-H.; Liu, S.-I.; SHEN-IUAN LIU ; CHUNG-PING CHEN | IEEE Journal of Solid-State Circuits | 19 | 19 | |