公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2016 | OpenDesign flow database: The infrastructure for VLSI design and design automation research | Jung, J.; Jiang, I.H.-R.; Nam, G.-J.; Kravets, V.N.; Behjat, L.; Li, Y.-L.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2012 | Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. | Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang; HUI-RU JIANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | | | |
2019 | Openmpl: An open source layout decomposer: Invited paper | Li, W.; Ma, Y.; Sun, Q.; Lin, Y.; Jiang, I.H.-R.; Yu, B.; Pan, D.Z.; HUI-RU JIANG | Proceedings of International Conference on ASIC | | | |
2021 | OpenMPL: An Open-Source Layout Decomposer | Li W; Ma Y; Sun Q; Zhang L; Lin Y; Jiang I.H.-R; Yu B; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 5 | 4 | |
2021 | Opportunities for 2.5/3D Heterogeneous SoC Integration | CHUNG-PING CHEN ; HUI-RU JIANG ; JIUN-LANG HUANG ; YAO-WEN CHANG | 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings | 1 | 0 | |
2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
2010 | Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles | Jiang, I.H.-R.; Chang, H.-Y.; Chang, C.-L.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | | | |
1999 | Optimum loading dispersion for high-speed tree-type decision circuitry. | Jiang, Jie-Hong Roland; JIE-HONG JIANG ; HUI-RU JIANG | Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999 | 0 | 0 | |
2013 | The overview of 2013 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | | | |
2014 | The overview of 2014 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 | | | |
2016 | OWARU: Free space-aware timing-driven incremental placement | Jung, J.; Nam, G.-J.; Reddy, L.; Jiang, I.H.-R.; Shin, Y.; HUI-RU JIANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2018 | OWARU: Free space-aware timing-driven incremental placement with critical path smoothing | Jinwook Jung; Gi-Joon Nam; Lakshmi N. Reddy; Iris Hui-Ru Jiang; Youngsoo Shin; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) | 7 | 5 | |
2007 | Performance constraints aware voltage Islands generation in SoC floorplan design | Lu, M.-C.; Wu, M.-C.; Chen, H.-M.; HUI-RU JIANG | 2006 IEEE International Systems-on-Chip Conference, SOC | | | |
0 | Please see http://dblp.uni-trier.de/pers/hd/j/Jiang:Iris_Hui=Ru | Iris Hui-Ru Jiang; HUI-RU JIANG ; 江蕙如 | | | | |
2009 | POSA: Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | Proceedings - IEEE International Symposium on Circuits and Systems | | | |
2017 | Power and area efficient hold time fixing by free metal segment allocation | Wei-Lun Chiu; Iris Hui-Ru Jiang; Chien-Pang Lu; Yu-Tung Chang; HUI-RU JIANG ; 江蕙如 | 54th ACM/EDAC/IEEE Design Automation Conference (DAC-2017) | 1 | 0 | |
2024 | Power Sub-Mesh Construction in Multiple Power Domain Design with IR Drop and Routability Optimization | Lu, Chien Pang; HUI-RU JIANG ; Peng, Chung Ching; Mohd Razha, Mohd Mawardi; Uber, Alessandro | Proceedings of the International Symposium on Physical Design | | | |
2008 | Power-state-aware buffered tree construction | Jiang, I.H.-R.; Wu, M.-H.; HUI-RU JIANG | 26th IEEE International Conference on Computer Design 2008, ICCD | | | |
2013 | Pulsed-latch replacement using concurrent time borrowing and clock gating | Chang, C.-L.; HUI-RU JIANG | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | | | |
2013 | PushPull: Short path padding for timing error resilient circuits | Yang, Y.-M.; Jiang, I.H.-R.; Ho, S.-T.; HUI-RU JIANG | Proceedings of the International Symposium on Physical Design | | | |