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J. B. Kuo
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Showing results 54 to 73 of 102
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Issue Date
Title
Author(s)
Source
scopus
WOS
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2006
Gate capacitances behavior of nanometer FD SOI CMOS devices with HfO2 high-k gate dielectric considering vertical and fringing displacement effects using 2-D simulation
Y. S. Lin; C. H. Lin; J. B. Kuo; K. W. Su; JAMES-B KUO
IEEE Transactions on Electron Devices
6
5
2004
Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate
J. B. Kuo; C. H. Hsu; C. P. Yang; JAMES-B KUO
IEEE Conference on Electron Devices and Solid-State Circuits
3
0
2010
Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect
H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
Microelectronics Reliability
5
6
2009
Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect
H. J. Hung; J. B. Kuo; D. Chen; C. S. Yeh; JAMES-B KUO
International Electron Devices Materials Symposium
2006
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology
B. Chung; J. B. Kuo; JAMES-B KUO
ISCAS
0
0
2006
Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique
B. Chung; J. B. Kuo; JAMES-B KUO
PATMOS
2008
Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications
R. Chen; R. Liu; J. B. Kuo; JAMES-B KUO
ICSICT
1
0
2005
Gate-Misalignment Related Capacitance Behavior of a 100nm DG SOI MOS Devices with N+/p+ Top/Bottom Gate
J. B. KUo; C. H. Hsu; C. P. Yang; JAMES-B KUO
HKEDSSC
2012
Grain Boundary-Related Kink Effects of Poly-Si TFTs
T. C. Liu; J. B. Kuo; JAMES-B KUO
IEEE International Conference on Electron Devices and Solid State Circuit
1
0
2012
Grain-Boundary Impact Ionization-Induced Current Hump Effects of Polysilicon TFTs
T. C. Liu; J. B. Kuo; S. Zhang; JAMES-B KUO
IEDMS
2002
High-Temperature Quasi-Saturation Model of High-Voltage DMOS Power Devices
C. L. Yang; J. B. Kuo; JAMES-B KUO
Hong Kong Electron Devices Meeting
0
0
2014
Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC
G. Lin; C. B. Hsu; J. B. Kuo; JAMES-B KUO
Asia Pacific CSEE Conference
1999
Low-Voltage CMOS VLSI Circuits
J. B. Kuo; J. H. Lou; JAMES-B KUO
2001
Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques
J. B. Kuo; S. C. Liu; JAMES-B KUO
2007
Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic
E. K. Loo; J. B. Kuo; M. Syrzycki; JAMES-B KUO
Canadian Conference on Electrical and Computer Engineering
2010
Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications
W.C.H. Lin; J. B. Kuo; JAMES-B KUO
ISCAS
0
0
2001
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2004
Low-Voltage SOI CMOS VLSI Devices and Circuits
J. B. Kuo; S. C. Lin; JAMES-B KUO
2012
Modeling Hot-Carrier-Induced Reliability of Poly-silicon Thin Film Transistors
L. L. Wang; J. B. Kuo; S. Zhang; JAMES-B KUO
IEEE International Conference on Electron Devices and Solid State Circuit
0
0
2001
Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model
J. B. Kuo; S. C. Lin; JAMES-B KUO
International Conference on Semiconductor IC Technology (ICSICT)
1
0